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Wed, 26 May 2021 12:56:26 +0200 Received: from localhost.localdomain (172.16.51.17) by DHPWEX01.DH-ELECTRONICS.ORG (10.64.2.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12 via Frontend Transport; Wed, 26 May 2021 12:56:25 +0200 From: Christoph Niedermaier To: CC: Christoph Niedermaier , Shawn Guo , Fabio Estevam , Marek Vasut , NXP Linux Team , Subject: [PATCH 09/20] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl Date: Wed, 26 May 2021 12:54:06 +0200 Message-ID: <20210526105417.52996-10-cniedermaier@dh-electronics.com> X-Mailer: git-send-email 2.11.0 X-klartext: yes In-Reply-To: <20210526105417.52996-1-cniedermaier@dh-electronics.com> References: <20210526105417.52996-1-cniedermaier@dh-electronics.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210526_045732_088750_DF6B786E X-CRM114-Status: GOOD ( 12.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to the SoM devicetree. Add PCIe Reset GPIO to the board devicetree. Signed-off-by: Christoph Niedermaier Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org --- arch/arm/boot/dts/imx6q-dhcom-pdk2.dts | 7 +++---- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 11 +++++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index a685b1c3208f..6c5eaeefa22e 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -232,9 +232,9 @@ >; }; - pinctrl_pcie: pcie-grp { + pinctrl_pcie_reset: pcie-reset-grp { fsl,pins = < - MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x120b0 >; }; }; @@ -244,8 +244,7 @@ }; &pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie>; + pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>; reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index fbc2b3e031b8..66a32b4b8214 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -449,6 +449,12 @@ >; }; + pinctrl_pcie: pcie-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* Wake */ + >; + }; + pinctrl_uart1: uart1-grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -567,6 +573,11 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; +}; + ®_arm { vin-supply = <&sw3_reg>; };