[18/20] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2

Message ID	20210526105417.52996-19-cniedermaier@dh-electronics.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=ydQD=KV=lists.infradead.org=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 07E24613F9 From: Christoph Niedermaier <cniedermaier@dh-electronics.com> To: <linux-arm-kernel@lists.infradead.org> CC: Christoph Niedermaier <cniedermaier@dh-electronics.com>, Shawn Guo <shawnguo@kernel.org>, Fabio Estevam <festevam@gmail.com>, Marek Vasut <marex@denx.de>, NXP Linux Team <linux-imx@nxp.com>, <kernel@dh-electronics.com> Subject: [PATCH 18/20] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2 Date: Wed, 26 May 2021 12:54:15 +0200 Message-ID: <20210526105417.52996-19-cniedermaier@dh-electronics.com> In-Reply-To: <20210526105417.52996-1-cniedermaier@dh-electronics.com> References: <20210526105417.52996-1-cniedermaier@dh-electronics.com> MIME-Version: 1.0 Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org
Series	ARM: dts: imx6q-dhcom: Fix/update PDK2 board and adding PicoITX and DRC02 board \| expand [00/20] ARM: dts: imx6q-dhcom: Fix/update PDK2 board and adding PicoITX and DRC02 board [01/20] ARM: dts: imx6q-dhcom: Fix ethernet reset time properties [02/20] ARM: dts: imx6q-dhcom: Fix ethernet plugin detection problems [03/20] ARM: dts: imx6q-dhcom: Add gpios pinctrl for i2c bus recovery [04/20] ARM: dts: imx6q-dhcom: Add aliases for i2c, serial and rtc [05/20] ARM: dts: imx6q-dhcom: Add ethernet VIO regulator [06/20] ARM: dts: imx6q-dhcom: Add the parallel system bus [07/20] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY [08/20] ARM: dts: imx6q-dhcom: Fill GPIO line names on DHCOM SoM [09/20] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl [10/20] ARM: dts: imx6q-dhcom: Align stdout-path with other DHCOM SoMs [11/20] ARM: dts: imx6q-dhcom: Add keys and leds to the PDK2 board [12/20] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board [13/20] ARM: dts: imx6q-dhcom: Rework of the DHCOM GPIO pinctrls [14/20] ARM: dts: imx6q-dhcom: Remove ddc-i2c-bus property [15/20] ARM: dts: imx6q-dhcom: Set minimum memory size of all DHCOM i.MX6 variants [16/20] ARM: dts: imx6q-dhcom: Rearrange of iomux [17/20] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees [18/20] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2 [19/20] ARM: dts: imx6qdl-dhcom: Add DHCOM based PicoITX board [20/20] ARM: dts: imx6qdl-dhcom: Add DHSOM based DRC02 board

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts index a285faf24bbc..d4d57370615d 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts @@ -2,375 +2,24 @@ /* * Copyright (C) 2015-2021 DH electronics GmbH * Copyright (C) 2018 Marek Vasut <marex@denx.de> + * + * DHCOM iMX6 variant: + * DHCM-iMX6Q-C0800-R102-F0819-E-SD-RTC-T-HS-I-01D2 + * DHCOM PCB number: 493-300 or newer + * PDK2 PCB number: 516-400 or newer */ - /dts-v1/; -#include "imx6q-dhcom-som.dtsi" +#include "imx6q.dtsi" +#include "imx6qdl-dhcom-som.dtsi" +#include "imx6qdl-dhcom-pdk2.dtsi" / { - model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)"; - compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q"; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - clk_ext_audio_codec: clock-codec { - #clock-cells = <0>; - clock-frequency = <24000000>; - compatible = "fixed-clock"; - }; - - display_bl: display-bl { - brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; - compatible = "pwm-backlight"; - default-brightness-level = <8>; - enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ - pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; - status = "okay"; - }; - - lcd_display: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; - pinctrl-names = "default"; - status = "okay"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - gpio-keys { - #size-cells = <0>; - compatible = "gpio-keys"; - - button-0 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ - label = "TA1-GPIO-A"; - linux,code = <KEY_A>; - pinctrl-0 = <&pinctrl_dhcom_a>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-1 { - gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ - label = "TA2-GPIO-B"; - linux,code = <KEY_B>; - pinctrl-0 = <&pinctrl_dhcom_b>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-2 { - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ - label = "TA3-GPIO-C"; - linux,code = <KEY_C>; - pinctrl-0 = <&pinctrl_dhcom_c>; - pinctrl-names = "default"; - wakeup-source; - }; - - button-3 { - gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ - label = "TA4-GPIO-D"; - linux,code = <KEY_D>; - pinctrl-0 = <&pinctrl_dhcom_d>; - pinctrl-names = "default"; - wakeup-source; - }; - }; - - led { - compatible = "gpio-leds"; - - /* - * Disable led5, because GPIO E is - * already used as touch interrupt. - */ - led-0 { - default-state = "off"; - gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ - label = "green:led5"; - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - status = "disabled"; - }; - - led-1 { - default-state = "off"; - gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ - label = "green:led6"; - pinctrl-0 = <&pinctrl_dhcom_f>; - pinctrl-names = "default"; - }; - - led-2 { - default-state = "off"; - gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ - label = "green:led7"; - pinctrl-0 = <&pinctrl_dhcom_h>; - pinctrl-names = "default"; - }; - - led-3 { - default-state = "off"; - gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ - label = "green:led8"; - pinctrl-0 = <&pinctrl_dhcom_i>; - pinctrl-names = "default"; - }; - }; - - panel { - backlight = <&display_bl>; - compatible = "edt,etm0700g0edh6"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - sound { - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE_IN", "Line In Jack", - "Headphone Jack", "HP_OUT"; - compatible = "fsl,imx-audio-sgtl5000"; - model = "imx-sgtl5000"; - mux-ext-port = <3>; - mux-int-port = <1>; - ssi-controller = <&ssi1>; - }; -}; - -&audmux { - pinctrl-0 = <&pinctrl_audmux_ext>; - pinctrl-names = "default"; - status = "okay"; -}; - -&can1 { - status = "okay"; -}; - -&can2 { - status = "disabled"; -}; - -/* 1G ethernet */ -/delete-node/ &ethphy0; -&fec { - phy-mode = "rgmii"; - phy-handle = <&ethphy7>; - pinctrl-0 = <&pinctrl_enet_1G>; - pinctrl-names = "default"; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy7: ethernet-phy@7 { /* KSZ 9021 */ - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - max-speed = <1000>; - pinctrl-0 = <&pinctrl_ethphy7>; - pinctrl-names = "default"; - reg = <7>; - reset-assert-us = <1000>; - reset-deassert-us = <1000>; - reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; - - rxc-skew-ps = <3000>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - rxdv-skew-ps = <0>; - txc-skew-ps = <3000>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - txen-skew-ps = <0>; - }; - }; -}; - -&hdmi { - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c2 { - sgtl5000: codec@a { - #sound-dai-cells = <0>; - clocks = <&clk_ext_audio_codec>; - compatible = "fsl,sgtl5000"; - reg = <0x0a>; - VDDA-supply = <&reg_3p3v>; - VDDIO-supply = <&sw2_reg>; - }; - - touchscreen@38 { - compatible = "edt,edt-ft5406"; - interrupt-parent = <&gpio4>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ - pinctrl-0 = <&pinctrl_dhcom_e>; - pinctrl-names = "default"; - reg = <0x38>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&lcd_display_in>; -}; - -&pcie { - pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; - reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pinctrl_pwm1>; - pinctrl-names = "default"; - status = "okay"; -}; - -&ssi1 { - status = "okay"; + model = "DH electronics i.MX6Q DHCOM on Premium Developer Kit (2)"; + compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", + "fsl,imx6q"; }; &sata { status = "okay"; }; - -&usdhc3 { /* Micro SD card on module */ - status = "okay"; -}; - -&iomuxc { - pinctrl-0 = < - /* - * The following DHCOM GPIOs are used on this board. - * Therefore, they have been removed from the list below. - * A: key TA1 - * B: key TA2 - * C: key TA3 - * D: key TA4 - * E: touchscreen - * F: led6 - * G: backlight enable - * H: led7 - * I: led8 - * J: PCIe reset - */ - &pinctrl_hog_base - &pinctrl_dhcom_k &pinctrl_dhcom_l - &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o - &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r - &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u - &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int - >; - pinctrl-names = "default"; - - pinctrl_audmux_ext: audmux-ext-grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 - >; - }; - - pinctrl_enet_1G: enet-1G-grp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - >; - }; - - pinctrl_ethphy7: ethphy7-grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ - >; - }; - - pinctrl_ipu1_lcdif: ipu1-lcdif-grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 - >; - }; - - pinctrl_pwm1: pwm1-grp { - fsl,pins = < - MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi new file mode 100644 index 000000000000..61191f38e735 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-dhcom-pdk2.dtsi @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2021 DH electronics GmbH + * Copyright (C) 2018 Marek Vasut <marex@denx.de> + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + clk_ext_audio_codec: clock-codec { + #clock-cells = <0>; + clock-frequency = <24000000>; + compatible = "fixed-clock"; + }; + + display_bl: display-bl { + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + compatible = "pwm-backlight"; + default-brightness-level = <8>; + enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */ + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + status = "okay"; + }; + + lcd_display: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>; + pinctrl-names = "default"; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + gpio-keys { + #size-cells = <0>; + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = <KEY_A>; + pinctrl-0 = <&pinctrl_dhcom_a>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-1 { + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = <KEY_B>; + pinctrl-0 = <&pinctrl_dhcom_b>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-2 { + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = <KEY_C>; + pinctrl-0 = <&pinctrl_dhcom_c>; + pinctrl-names = "default"; + wakeup-source; + }; + + button-3 { + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = <KEY_D>; + pinctrl-0 = <&pinctrl_dhcom_d>; + pinctrl-names = "default"; + wakeup-source; + }; + }; + + led { + compatible = "gpio-leds"; + + /* + * Disable led5, because GPIO E is + * already used as touch interrupt. + */ + led-0 { + default-state = "off"; + gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */ + label = "green:led5"; + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + status = "disabled"; + }; + + led-1 { + default-state = "off"; + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */ + label = "green:led6"; + pinctrl-0 = <&pinctrl_dhcom_f>; + pinctrl-names = "default"; + }; + + led-2 { + default-state = "off"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */ + label = "green:led7"; + pinctrl-0 = <&pinctrl_dhcom_h>; + pinctrl-names = "default"; + }; + + led-3 { + default-state = "off"; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + label = "green:led8"; + pinctrl-0 = <&pinctrl_dhcom_i>; + pinctrl-names = "default"; + }; + }; + + panel { + backlight = <&display_bl>; + compatible = "edt,etm0700g0edh6"; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + sound { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx-sgtl5000"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; +}; + +&audmux { + pinctrl-0 = <&pinctrl_audmux_ext>; + pinctrl-names = "default"; + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "disabled"; +}; + +/* 1G ethernet */ +/delete-node/ &ethphy0; +&fec { + phy-mode = "rgmii"; + phy-handle = <&ethphy7>; + pinctrl-0 = <&pinctrl_enet_1G>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy7: ethernet-phy@7 { /* KSZ 9021 */ + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + max-speed = <1000>; + pinctrl-0 = <&pinctrl_ethphy7>; + pinctrl-names = "default"; + reg = <7>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; + + rxc-skew-ps = <3000>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + rxdv-skew-ps = <0>; + txc-skew-ps = <3000>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + txen-skew-ps = <0>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c2 { + sgtl5000: codec@a { + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <&reg_3p3v>; + VDDIO-supply = <&sw2_reg>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + pinctrl-0 = <&pinctrl_dhcom_e>; + pinctrl-names = "default"; + reg = <0x38>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&lcd_display_in>; +}; + +&pcie { + pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>; + reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */ + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&usdhc2 { /* SD card */ + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = < + /* + * The following DHCOM GPIOs are used on this board. + * Therefore, they have been removed from the list below. + * A: key TA1 + * B: key TA2 + * C: key TA3 + * D: key TA4 + * E: touchscreen + * F: led6 + * G: backlight enable + * H: led7 + * I: led8 + * J: PCIe reset + */ + &pinctrl_hog_base + &pinctrl_dhcom_k &pinctrl_dhcom_l + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u + &pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int + >; + pinctrl-names = "default"; + + pinctrl_audmux_ext: audmux-ext-grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + >; + }; + + pinctrl_enet_1G: enet-1G-grp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 + >; + }; + + pinctrl_ethphy7: ethphy7-grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0xb1 /* WOL */ + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0xb0 /* Reset */ + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0xb1 /* Int */ + >; + }; + + pinctrl_ipu1_lcdif: ipu1-lcdif-grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi similarity index 97% rename from arch/arm/boot/dts/imx6q-dhcom-som.dtsi rename to arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi index 6721f9f67513..953d749596dd 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dhcom-som.dtsi @@ -4,7 +4,6 @@ * Copyright (C) 2018 Marek Vasut <marex@denx.de> */ -#include "imx6q.dtsi" #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/imx6qdl-clock.h> @@ -81,18 +80,20 @@ &can1 { pinctrl-0 = <&pinctrl_flexcan1>; pinctrl-names = "default"; + status = "okay"; }; /* - * Special hardware required which uses the pins from micro SD card. The pins - * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx - * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board - * device tree file, you also need to disable the micro SD card and the uart1 - * rts/cts have to be disabled or output on other DHCOM pins. + * Special SoM hardware required which uses the pins from micro SD card. The + * pins SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 + * Tx and Rx are routed to the DHCOM UART1 rts/cts pins. So to enable can2 on + * the board device tree file, the micro SD card must be disabled and the uart1 + * rts/cts must be disabled or output on other DHCOM pins. */ &can2 { pinctrl-0 = <&pinctrl_flexcan2>; pinctrl-names = "default"; + status = "disabled"; }; &ecspi1 { @@ -115,7 +116,7 @@ cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; pinctrl-0 = <&pinctrl_ecspi2>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &fec { @@ -334,6 +335,11 @@ pinctrl-names = "default"; }; +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + &reg_arm { vin-supply = <&sw3_reg>; }; @@ -400,7 +406,7 @@ keep-power-in-suspend; pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-names = "default"; - status = "okay"; + status = "disabled"; }; &usdhc3 { /* Micro SD card on module */ @@ -409,7 +415,7 @@ keep-power-in-suspend; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-names = "default"; - status = "disabled"; + status = "okay"; }; &usdhc4 { /* eMMC on module */ @@ -672,6 +678,12 @@ >; }; + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 + >; + }; + pinctrl_rtc: rtc-grp { fsl,pins = < MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x120b0

[18/20] ARM: dts: imx6qdl-dhcom: Split SoC-independent parts of DHCOM SOM and PDK2

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Patch