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[176.141.241.253]) by smtp.gmail.com with ESMTPSA id h14sm23841045wmb.1.2021.05.30.00.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 May 2021 00:27:07 -0700 (PDT) From: Romain Perier To: Wim Van Sebroeck , Guenter Roeck , Rob Herring Cc: Daniel Palmer , Mohammed Billoo , linux-watchdog@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] ARM: dts: mstar: Add watchdog device_node definition Date: Sun, 30 May 2021 09:26:45 +0200 Message-Id: <20210530072645.10379-4-romain.perier@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210530072645.10379-1-romain.perier@gmail.com> References: <20210530072645.10379-1-romain.perier@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210530_002709_441113_11D42DB9 X-CRM114-Status: GOOD ( 10.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This adds the definition of both an oscillator at 12Mhz required by the the watchdog and the watchdog device_node. Signed-off-by: Romain Perier --- arch/arm/boot/dts/mstar-v7.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index 3d5d8c634de3..23dff8fe4731 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -62,6 +62,14 @@ rtc_xtal: rtc_xtal { clock-frequency = <32768>; status = "disabled"; }; + + xtal_div2: xtal_div2 { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&xtal>; + clock-div = <2>; + clock-mult = <1>; + }; }; soc: soc { @@ -119,6 +127,12 @@ pm_irin_pins: pm_irin { }; }; + watchdog: watchdog@6000 { + compatible = "mstar,msc313e-wdt"; + reg = <0x6000 0x1f>; + clocks = <&xtal_div2>; + }; + intc_fiq: interrupt-controller@201310 { compatible = "mstar,mst-intc"; reg = <0x201310 0x40>;