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[89.103.215.157]) by smtp.gmail.com with ESMTPSA id h9sm6238376edt.18.2021.05.30.21.46.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 May 2021 21:46:18 -0700 (PDT) From: Roman Beranek X-Google-Original-From: Roman Beranek To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: Thierry Reding , Emil Lenngren , Pascal Roeleven , Lee Jones , Maxime Ripard , Chen-Yu Tsai , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com Subject: [PATCH 1/6] pwm: sun4i: enable clk prior to getting its rate Date: Mon, 31 May 2021 06:46:03 +0200 Message-Id: <20210531044608.1006024-2-roman.beranek@prusa3d.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210531044608.1006024-1-roman.beranek@prusa3d.com> References: <20210531044608.1006024-1-roman.beranek@prusa3d.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210530_214621_454934_86FC0446 X-CRM114-Status: GOOD ( 11.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Ensure the PWM clock is enabled prior to retrieving its rate, as is already being done in sun4i_pwm_apply. Signed-off-by: Roman Beranek --- drivers/pwm/pwm-sun4i.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index e01becd102c0..3721b9894cf6 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -117,8 +117,15 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, u64 clk_rate, tmp; u32 val; unsigned int prescaler; + int ret; + ret = clk_prepare_enable(sun4i_pwm->clk); + if (ret) { + dev_err(chip->dev, "failed to enable PWM clock\n"); + return; + } clk_rate = clk_get_rate(sun4i_pwm->clk); + clk_disable_unprepare(sun4i_pwm->clk); val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);