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[89.103.215.157]) by smtp.gmail.com with ESMTPSA id h9sm6238376edt.18.2021.05.30.21.46.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 May 2021 21:46:19 -0700 (PDT) From: Roman Beranek X-Google-Original-From: Roman Beranek To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= Cc: Thierry Reding , Emil Lenngren , Pascal Roeleven , Lee Jones , Maxime Ripard , Chen-Yu Tsai , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com Subject: [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay Date: Mon, 31 May 2021 06:46:04 +0200 Message-Id: <20210531044608.1006024-3-roman.beranek@prusa3d.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210531044608.1006024-1-roman.beranek@prusa3d.com> References: <20210531044608.1006024-1-roman.beranek@prusa3d.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210530_214621_449111_5E746AE0 X-CRM114-Status: GOOD ( 12.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The reason why we wait before gating the clock is to allow for the PWM to finish its cycle and stop. But it won't stop unless the EN bit is disabled. Signed-off-by: Roman Beranek --- drivers/pwm/pwm-sun4i.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 3721b9894cf6..2777abe66f79 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -303,6 +303,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, if (state->enabled) ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); + else + ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); @@ -325,7 +327,6 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); - ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock);