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Mon, 31 May 2021 13:20:53 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 31 May 2021 06:20:37 -0700 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Mon, 31 May 2021 06:20:37 -0700 Received: from [10.140.6.25] (port=53014 helo=xhdnagasure40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lnhqN-0004GE-C6; Mon, 31 May 2021 06:20:35 -0700 From: Raviteja Narayanam To: , CC: , , , , Raviteja Narayanam Subject: [PATCH 03/10] i2c: xiic: Fix coding style issues Date: Mon, 31 May 2021 07:19:41 -0600 Message-ID: <20210531131948.19477-4-raviteja.narayanam@xilinx.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210531131948.19477-1-raviteja.narayanam@xilinx.com> References: <20210531131948.19477-1-raviteja.narayanam@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3a7227ed-ec0a-480d-cd18-08d92436eb0d X-MS-TrafficTypeDiagnostic: BN6PR02MB2660: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:133; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 May 2021 13:20:53.9220 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a7227ed-ec0a-480d-cd18-08d92436eb0d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0060.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2660 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210531_062106_390538_F3183546 X-CRM114-Status: GOOD ( 25.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Michal Simek Most of these stuff are reported by checkpatch. But fixes are: - Incorrect indetation - Missing blank line after variable declaration - Additional () - Missing spaces around + - Else after if with return - Missing parenthesis when if has them - Newlines - Remove MODULE_ALIAS - none is really using it - Changing msleep to usleep_range - Other trivial fixes Signed-off-by: Michal Simek Signed-off-by: Raviteja Narayanam --- drivers/i2c/busses/i2c-xiic.c | 69 +++++++++++++++++------------------ 1 file changed, 34 insertions(+), 35 deletions(-) diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c index 004103267e9c..fa2eef9e622f 100644 --- a/drivers/i2c/busses/i2c-xiic.c +++ b/drivers/i2c/busses/i2c-xiic.c @@ -69,7 +69,7 @@ struct xiic_i2c { wait_queue_head_t wait; struct i2c_adapter adap; struct i2c_msg *tx_msg; - struct mutex lock; + struct mutex lock; /* Locking between isr and new xfer */ unsigned int tx_pos; unsigned int nmsgs; struct i2c_msg *rx_msg; @@ -82,24 +82,23 @@ struct xiic_i2c { bool prev_msg_tx; }; - #define XIIC_MSB_OFFSET 0 -#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) +#define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) /* * Register offsets in bytes from RegisterBase. Three is added to the * base offset to access LSB (IBM style) of the word */ -#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ -#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ -#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ -#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ -#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ -#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ -#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ -#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ -#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ -#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ +#define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ +#define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ +#define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ +#define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ +#define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ +#define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ +#define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ +#define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ +#define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ +#define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ /* Control Register masks */ #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ @@ -237,18 +236,21 @@ static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) { u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); + xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); } static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) { u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); + xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); } static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) { u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); + xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); } @@ -418,7 +420,8 @@ static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) while (len--) { u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; - if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { + + if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { /* last message in transfer -> STOP */ data |= XIIC_TX_DYN_STOP_MASK; dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); @@ -519,8 +522,8 @@ static irqreturn_t xiic_process(int irq, void *dev_id) /* Service requesting interrupt */ if ((pend & XIIC_INTR_ARB_LOST_MASK) || - ((pend & XIIC_INTR_TX_ERROR_MASK) && - !(pend & XIIC_INTR_RX_FULL_MASK))) { + ((pend & XIIC_INTR_TX_ERROR_MASK) && + !(pend & XIIC_INTR_RX_FULL_MASK))) { /* bus arbritration lost, or... * Transmit error _OR_ RX completed * if this happens when RX_FULL is not set @@ -662,9 +665,8 @@ static int xiic_busy(struct xiic_i2c *i2c) * should ignore it, since bus will never be released and i2c will be * stuck forever. */ - if (i2c->singlemaster) { + if (i2c->singlemaster) return 0; - } /* for instance if previous transfer was terminated due to TX error * it might be that the bus is on it's way to become available @@ -672,7 +674,7 @@ static int xiic_busy(struct xiic_i2c *i2c) */ err = xiic_bus_busy(i2c); while (err && tries--) { - msleep(1); + usleep_range(1000, 2000); err = xiic_bus_busy(i2c); } @@ -867,7 +869,6 @@ static void xiic_start_send(struct xiic_i2c *i2c) xiic_std_fill_tx_fifo(i2c); if ((cr & XIIC_CR_MSMS_MASK) == 0) { - /* Start Tx by writing to CR */ cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr | @@ -891,9 +892,6 @@ static irqreturn_t xiic_isr(int irq, void *dev_id) /* Do not processes a devices interrupts if the device has no * interrupts pending */ - - dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); - isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); pend = isr & ier; @@ -907,6 +905,7 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) { int first = 1; int fifo_space = xiic_tx_fifo_space(i2c); + dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", __func__, i2c->tx_msg, fifo_space); @@ -921,19 +920,20 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) i2c->nmsgs--; i2c->tx_msg++; i2c->tx_pos = 0; - } else + } else { first = 0; + } if (i2c->tx_msg->flags & I2C_M_RD) { /* we dont date putting several reads in the FIFO */ xiic_start_recv(i2c); return; - } else { - xiic_start_send(i2c); - if (xiic_tx_space(i2c) != 0) { - /* the message could not be completely sent */ - break; - } + } + + xiic_start_send(i2c); + if (xiic_tx_space(i2c) != 0) { + /* the message could not be completely sent */ + break; } fifo_space = xiic_tx_fifo_space(i2c); @@ -944,12 +944,12 @@ static void __xiic_start_xfer(struct xiic_i2c *i2c) */ if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); - } static int xiic_start_xfer(struct xiic_i2c *i2c) { int ret; + mutex_lock(&i2c->lock); ret = xiic_reinit(i2c); @@ -1001,8 +1001,8 @@ static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) goto out; } - if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || - (i2c->state == STATE_DONE), HZ)) { + if (wait_event_timeout(i2c->wait, i2c->state == STATE_ERROR || + i2c->state == STATE_DONE, HZ)) { err = (i2c->state == STATE_DONE) ? num : -EIO; goto out; } else { @@ -1035,7 +1035,6 @@ static const struct i2c_adapter xiic_adapter = { .algo = &xiic_algorithm, }; - static int xiic_i2c_probe(struct platform_device *pdev) { struct xiic_i2c *i2c; @@ -1195,6 +1194,7 @@ static const struct dev_pm_ops xiic_dev_pm_ops = { SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, xiic_i2c_runtime_resume, NULL) }; + static struct platform_driver xiic_i2c_driver = { .probe = xiic_i2c_probe, .remove = xiic_i2c_remove, @@ -1210,4 +1210,3 @@ module_platform_driver(xiic_i2c_driver); MODULE_AUTHOR("info@mocean-labs.com"); MODULE_DESCRIPTION("Xilinx I2C bus driver"); MODULE_LICENSE("GPL v2"); -MODULE_ALIAS("platform:"DRIVER_NAME);