diff mbox series

[27/27] arm64: dts: mt8195: add cpufreq device nodes

Message ID 20210615173233.26682-27-tinghan.shen@mediatek.com (mailing list archive)
State New, archived
Headers show
Series [01/27] arm64: dts: mt8195: add infracfg_rst node | expand

Commit Message

Tinghan Shen June 15, 2021, 5:32 p.m. UTC 
From: YT Lee <yt.lee@mediatek.corp-partner.google.com>

this 8195 cpufreq device nodes is based on below dt-bindings document
https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-3-git-send-email-hector.yuan@mediatek.com/

and it also rely on below patches to work
[1]https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-2-git-send-email-hector.yuan@mediatek.com/
[2]https://patchwork.kernel.org/project/linux-pm/patch/20201105125001.32473-1-lukasz.luba@arm.com/
[3]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-3-lukasz.luba@arm.com/
[4]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-4-lukasz.luba@arm.com/
[5]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-5-lukasz.luba@arm.com/

Signed-off-by: YT Lee <yt.lee@mediatek.corp-partner.google.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 25a6ee7c6659..e5ebf8d663df 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -54,6 +54,7 @@ 
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x000>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -66,6 +67,7 @@ 
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x100>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -78,6 +80,7 @@ 
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x200>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -90,6 +93,7 @@ 
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x300>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -102,6 +106,7 @@ 
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x400>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -114,6 +119,7 @@ 
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x500>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -126,6 +132,7 @@ 
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x600>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -138,6 +145,7 @@ 
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x700>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -257,6 +265,12 @@ 
 		method = "smc";
 	};
 
+	performance: performance-controller@11bc10 {
+		compatible = "mediatek,cpufreq-hw";
+		reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+		#performance-domain-cells = <1>;
+	};
+
 	timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;