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Thu, 17 Jun 2021 11:33:12 +0000 (GMT) From: Alim Akhtar To: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org Cc: krzysztof.kozlowski@canonical.com, linux-samsung-soc@vger.kernel.org, Alim Akhtar Subject: [PATCH 1/2] arm64: dts: exynos7: Add cpu cache information Date: Thu, 17 Jun 2021 17:07:38 +0530 Message-Id: <20210617113739.66911-1-alim.akhtar@samsung.com> X-Mailer: git-send-email 2.17.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrPIsWRmVeSWpSXmKPExsWy7bCmpu4049MJBm1/RCwezNvGZrHx7Q8m i02Pr7FaXN41h81ixvl9TBate4+wO7B5zGroZfPYtKqTzWPzknqPvi2rGD0+b5ILYI3isklJ zcksSy3St0vgynh0dA9rQZdgxf63e5gbGKfxdjFyckgImEic/X6JvYuRi0NIYDejxJXHy9hB EkICnxglDi9zhUh8ZpR4NuEFC0zHlp8vGSESuxglGi5vhXJamCRuLuxlBqliE9CWuDt9CxOI LSIQI/FwzzxWEJtZoFDiRctNoBUcHMICzhJ3DyaCmCwCqhJfNiqCVPAK2Eg0X7nIBrFLXmL1 hgPMIOMlBBaxS7y7vogJIuEica97OiuELSzx6vgWdghbSuLzu71sIDMlBLIlenYZQ4RrJJbO OwZ1v73EgStzWEBKmAU0Jdbv0ocIy0pMPbWOCeJIPone30+gNvFK7JgHY6tKNL+7CjVGWmJi dzfUBR4Sm59uZYaEW6zEscOX2Scwys5C2LCAkXEVo2RqQXFuemqxaYFRXmq5XnFibnFpXrpe cn7uJkZwnGt57WB8+OCD3iFGJg7GQ4wSHMxKIry6xScShHhTEiurUovy44tKc1KLDzFKc7Ao ifMuZT+UICSQnliSmp2aWpBaBJNl4uCUamAyWGl+2u2Us8tb07n+p+6kCubc0Oie/+lQ69cF HGySUpFbNb6KX97A+29GzPnH/PLVvHNvXePfP/ux2769ioG3+SUb2oX5J/qucQvcIlWadGDt uz6eS9tUElonvZ8elPnBaoJXnInHqSNv5O329u5z7q79PH3Pwj2qC54wz4j/+3594KGbDQn3 df7e2ynKp3ut8mnMfTat5sctHJUnZl8/t+Gh++8romf0S1LEeOVrfdjmO0jN28Hr2eZuVXMr 5dHTc/PlNh15HiHiePAB+6O4o09Mok38JF2VQ/YH5+/jN/livPtkYKyuxNLE80xN8maHmhdM vTPn41aHKcqnXsxoakx5+OowY6q/df+F34unKbEUZyQaajEXFScCAO+cjCxiAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrKJMWRmVeSWpSXmKPExsWy7bCSvO5Po9MJBjsWcVk8mLeNzWLj2x9M FpseX2O1uLxrDpvFjPP7mCxa9x5hd2DzmNXQy+axaVUnm8fmJfUefVtWMXp83iQXwBrFZZOS mpNZllqkb5fAlfHo6B7Wgi7Biv1v9zA3ME7j7WLk5JAQMJHY8vMlYxcjF4eQwA5GiebGWUwQ CWmJ6xsnsEPYwhIr/z1nhyhqYpJ4tvwYI0iCTUBb4u70LUANHBwiAnESreurQUxmgWKJ07/A osICzhJ3DyaCmCwCqhJfNiqC9PEK2Eg0X7nIBjFcXmL1hgPMExh5FjAyrGKUTC0ozk3PLTYs MMpLLdcrTswtLs1L10vOz93ECA4ZLa0djHtWfdA7xMjEwXiIUYKDWUmEV7f4RIIQb0piZVVq UX58UWlOavEhRmkOFiVx3gtdJ+OFBNITS1KzU1MLUotgskwcnFINTDq3os7bSMgnrub4UbCh 8ONTKyGh9nNz11YJ+N/ddmuS+r3SdrldcySVPBmulVxu29Z9eM+kbJ0F9cc+Hsr2umup8Lfz 9IP+mFPd/WGv9nl0eN+axMWg+nN7dDbfdKv30wzqvszJcfUI2vpFskgvy2Dmah/z/smmuzRe JtVu1W1hWPzqK1//HkOXFxfdp/1cpyu37M+hut3O5bwSbiX5S++fveBVUy0cIxbEHSwWKN3/ nMtNI2LVwTnWcj3FE7LS/y91S9CRUzrntnXGjNbbz65+cH1WuSzadObTH5+khHjMmzLK7+i5 NLjbZoap3366zHmN37374mklvpppmv9s/izJiiyTWi0/u+XhJPtbSizFGYmGWsxFxYkARUTM FogCAAA= X-CMS-MailID: 20210617113313epcas5p1fb3fff0b301b9e67a771349e72c2445b X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CMS-RootMailID: 20210617113313epcas5p1fb3fff0b301b9e67a771349e72c2445b References: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210617_043555_063418_59E7D389 X-CRM114-Status: GOOD ( 11.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds cpu caches information to its dt nodes so that the same is available to userspace via sysfs. This SoC has 48/32 KB I/D cache for each cores and 2MB of L2 cache. Signed-off-by: Alim Akhtar --- arch/arm64/boot/dts/exynos/exynos7.dtsi | 35 +++++++++++++++++++++++++ 1 file changed, 35 insertions(+) base-commit: 614124bea77e452aa6df7a8714e8bc820b489922 diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 10244e59d56d..8b06397ba6e7 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -54,6 +54,13 @@ compatible = "arm,cortex-a57"; reg = <0x0>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas1: cpu@1 { @@ -61,6 +68,13 @@ compatible = "arm,cortex-a57"; reg = <0x1>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas2: cpu@2 { @@ -68,6 +82,13 @@ compatible = "arm,cortex-a57"; reg = <0x2>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; }; cpu_atlas3: cpu@3 { @@ -75,6 +96,20 @@ compatible = "arm,cortex-a57"; reg = <0x3>; enable-method = "psci"; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&atlas_l2>; + }; + + atlas_l2: l2-cache0 { + compatible = "cache"; + cache-size = <0x200000>; + cache-line-size = <64>; + cache-sets = <2048>; }; };