From patchwork Sun Jun 20 13:49:53 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christine Zhu X-Patchwork-Id: 12333425 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C54AC49EA3 for ; Sun, 20 Jun 2021 13:52:26 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 55A1860C3D for ; Sun, 20 Jun 2021 13:52:26 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 55A1860C3D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=jN4lmMuIpSAm2uuEQoypKc1EUlsDnnYovqZGo3QsQ+0=; b=kxF1GPh1R55F5V pGJfdg7x59uQ1O83SOoiWaj5VVQdpSd71Ko0hXx2kcPZdXW8UKBS9zvpPvLQ6TUQJGqCk1z7W4fBJ oY6nu+wWZUt0XmVM523G1jRJ4TZwSkPrLAqCw8B3fRX8UERljnXIXH1HMww/PweEHynpoxdknn0gN t3jrL4CVCgpz145+23bP5xdASfUF0U/eJtfLXQwUPo5+5O5Xr6u382sZ38kCyYrM7gwZSbH8WKdD+ GLbahCFIWs8hxuOEEnnxpGwPwQ00bU1Q6ChOrCSbVbAXrLG8M4YDIsNxSm/SUvSqBh0a9jegN3VvJ Mj1Anjlt7xtJ49KonwNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1luxqL-0016sB-3O; Sun, 20 Jun 2021 13:50:33 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1luxpz-0016mi-Oh; Sun, 20 Jun 2021 13:50:15 +0000 X-UUID: fc9d92be0f6c4410b5df89a92f655986-20210620 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=nvc3cFYReASc8kiecK4+FVHUwEmkxg2AVL4VUrCJ6XI=; b=HOauLBMcW984ZGRMrOkYZI6+2aapakQf+iFIPgY9UMXnikAjlPUYl+hZMtC5bgncasnGJSU7Jqy05Pap5jL5ZhyS8ryUU1eRjAS8pk8x2KysfWPfHp//uoo2p3nnTGsyUrxCsfCZ+aL8dPhotoxUiSSvrXvVycdj5qB+ynyCti4=; X-UUID: fc9d92be0f6c4410b5df89a92f655986-20210620 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 609636575; Sun, 20 Jun 2021 06:50:09 -0700 Received: from mtkmbs08n2.mediatek.inc (172.21.101.56) by MTKMBS62DR.mediatek.inc (172.29.94.18) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 20 Jun 2021 06:50:07 -0700 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 20 Jun 2021 21:49:59 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 20 Jun 2021 21:49:58 +0800 From: Christine Zhu To: , , , CC: , , , , , , , , christine.zhu Subject: [v1,2/3] dt-binding: mt8195: add toprgu reset-controller head file Date: Sun, 20 Jun 2021 21:49:53 +0800 Message-ID: <20210620134954.15233-3-Christine.Zhu@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210620134954.15233-1-Christine.Zhu@mediatek.com> References: <20210620134954.15233-1-Christine.Zhu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210620_065011_855502_A49664C2 X-CRM114-Status: UNSURE ( 9.85 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "christine.zhu" add toprgu reset-controller head file for MT8195 platform Change-Id: Ib08da609e87d31ff0aa06b066f9797070931a693 Signed-off-by: christine.zhu --- include/dt-bindings/reset/mt8195-resets.h | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/reset/mt8195-resets.h diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h new file mode 100644 index 000000000000..620a594ee743 --- /dev/null +++ b/include/dt-bindings/reset/mt8195-resets.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Crystal Guo + */ + +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195 +#define _DT_BINDINGS_RESET_CONTROLLER_MT8195 + +#define MT8195_TOPRGU_CONN_MCU_SW_RST 0 +#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1 +#define MT8195_TOPRGU_APU_SW_RST 2 +#define MT8195_TOPRGU_INFRA_AO_GRST_SW_RST 6 +#define MT8195_TOPRGU_MMSYS_SW_RST 7 +#define MT8195_TOPRGU_MFG_SW_RST 8 +#define MT8195_TOPRGU_VENC_SW_RST 9 +#define MT8195_TOPRGU_VDEC_SW_RST 10 +#define MT8195_TOPRGU_IMG_SW_RST 11 +#define MT8195_TOPRGU_APMIXEDSYS_SW_RST 13 +#define MT8195_TOPRGU_AUDIO_SW_RST 14 +#define MT8195_TOPRGU_CAMSYS_SW_RST 15 +#define MT8195_TOPRGU_EDPTX_SW_RST 16 +#define MT8195_TOPRGU_ADSPSYS_SW_RST 21 +#define MT8195_TOPRGU_DPTX_SW_RST 22 +#define MT8195_TOPRGU_SPMI_MST_SW_RST 23 + +#define MT8195_TOPRGU_SW_RST_NUM 16 + +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */