| Message ID | 20210624021137.11513-1-mason.zhang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v4,1/1] arm64: dts: mediatek: add MT6779 spi master dts node | expand |
On Thu, 2021-06-24 at 10:11 +0800, Mason Zhang wrote: > From: Mason Zhang <Mason.Zhang@mediatek.com> > > This patch add spi master dts node for MT6779 SOC. > > Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 112 +++++++++++++++++++++++ > 1 file changed, 112 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > index 370f309d32de..c81e76865d1b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > @@ -219,6 +219,118 @@ > status = "disabled"; > }; > > + spi0: spi0@1100a000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x1100a000 0 0x1000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI0>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi1: spi1@11010000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11010000 0 0x1000>; > + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI1>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi2: spi2@11012000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11012000 0 0x1000>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI2>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi3: spi3@11013000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11013000 0 0x1000>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI3>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi4: spi4@11018000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11018000 0 0x1000>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI4>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi5: spi5@11019000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11019000 0 0x1000>; > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI5>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi6: spi6@1101d000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x1101d000 0 0x1000>; > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI6>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi7: spi7@1101e000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x1101e000 0 0x1000>; > + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI7>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > audio: clock-controller@11210000 { > compatible = "mediatek,mt6779-audio", "syscon"; > reg = <0 0x11210000 0 0x1000>; Dear Matthias: I'm sorry to disturb you again, My company mailbox has a little bug, it caused my comments always appearing in the commit message... I have update commit message now, so do you have any other concern about this patch? Can you help me gentle ping on this patch? Thanks Mason
On Thu, 2021-06-24 at 10:26 +0800, Mason Zhang wrote: > > Dear Matthias: > > I'm sorry to disturb you again, My company mailbox has a little bug, it > caused my comments always appearing in the commit message... > I have update commit message now, so do you have any other concern > about this patch? Can you help me gentle ping on this patch? > > Thanks > Mason Dear Matthias: Could you please gentle ping on this patch? Thanks Mason
On 24/06/2021 04:11, Mason Zhang wrote: > From: Mason Zhang <Mason.Zhang@mediatek.com> > > This patch add spi master dts node for MT6779 SOC. > > Signed-off-by: Mason Zhang <Mason.Zhang@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 112 +++++++++++++++++++++++ > 1 file changed, 112 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > index 370f309d32de..c81e76865d1b 100644 > --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi > @@ -219,6 +219,118 @@ > status = "disabled"; > }; > > + spi0: spi0@1100a000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; pad-select should be part of board DTS. > + reg = <0 0x1100a000 0 0x1000>; > + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI0>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; Should be disabled by default and enabled in board DTS. > + }; This gives me the following warning: arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi0@1100a000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi1@11010000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi2@11012000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi3@11013000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi4@11018000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi5@11019000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi6@1101d000:#interrupt-cells: size is (16), expected multiple of 12 arch/arm64/boot/dts/mediatek/mt6779.dtsi:145.4-27: Warning (interrupts_property): /soc/spi7@1101e000:#interrupt-cells: size is (16), expected multiple of 12 Regards, Matthias > + > + spi1: spi1@11010000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11010000 0 0x1000>; > + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI1>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi2: spi2@11012000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11012000 0 0x1000>; > + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI2>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi3: spi3@11013000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11013000 0 0x1000>; > + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI3>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi4: spi4@11018000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11018000 0 0x1000>; > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI4>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi5: spi5@11019000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x11019000 0 0x1000>; > + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI5>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi6: spi6@1101d000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x1101d000 0 0x1000>; > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI6>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > + spi7: spi7@1101e000 { > + compatible = "mediatek,mt6779-spi", > + "mediatek,mt6765-spi"; > + #address-cells = <1>; > + #size-cells = <0>; > + mediatek,pad-select = <0>; > + reg = <0 0x1101e000 0 0x1000>; > + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>; > + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, > + <&topckgen CLK_TOP_SPI>, > + <&infracfg_ao CLK_INFRA_SPI7>; > + clock-names = "parent-clk", "sel-clk", "spi-clk"; > + }; > + > audio: clock-controller@11210000 { > compatible = "mediatek,mt6779-audio", "syscon"; > reg = <0 0x11210000 0 0x1000>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi index 370f309d32de..c81e76865d1b 100644 --- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi @@ -219,6 +219,118 @@ status = "disabled"; }; + spi0: spi0@1100a000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi1: spi1@11010000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi2: spi2@11012000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi3: spi3@11013000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi4: spi4@11018000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi5: spi5@11019000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi6: spi6@1101d000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1101d000 0 0x1000>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI6>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + + spi7: spi7@1101e000 { + compatible = "mediatek,mt6779-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + mediatek,pad-select = <0>; + reg = <0 0x1101e000 0 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW 0>; + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_SPI7>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + }; + audio: clock-controller@11210000 { compatible = "mediatek,mt6779-audio", "syscon"; reg = <0 0x11210000 0 0x1000>;