From patchwork Thu Jun 24 03:43:36 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nobuhiro Iwamatsu X-Patchwork-Id: 12340767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 769F4C48BC2 for ; Thu, 24 Jun 2021 03:46:10 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 408F9613C5 for ; Thu, 24 Jun 2021 03:46:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 408F9613C5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=toshiba.co.jp Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=hkIFKXOscvrm05m0gpeB04kXPbYIHOiNuoxR8RkFktg=; b=VgvkW5yszQFqXM rmGTCur/StznxVf//o/809hdJQ+f04rWv4feogtvoEje5mhrg5Lix7m7jvQAxTwdPL2mA2b9UG+VY QRoDLRzfncBb58TYF6ZOeKQAyVuf/NN16+TkqwS5Qmp7x2ZMzJlnrTZvmyDlU27zFtx788ZERWZvC VJ3lJvE7lITz/5GLFB9aJnNC5UOQSKhrQoQr7qw7AaN/F8J0C0DVkuDtfZtI6gbv0gB9HVKZ64nVr ZTK7aLnrq0u98iuhTsI2uALsvFKmAdEk0MzkBG9pM8J8PlNjLAhz+IByTkdRUKf05WkyVgAS9RdGT vuewcbtOhr9EaznqNtfA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lwGHu-00CZ6M-GW; Thu, 24 Jun 2021 03:44:22 +0000 Received: from mo-csw1115.securemx.jp ([210.130.202.157] helo=mo-csw.securemx.jp) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lwGHX-00CZ27-Fk for linux-arm-kernel@lists.infradead.org; Thu, 24 Jun 2021 03:44:01 +0000 Received: by mo-csw.securemx.jp (mx-mo-csw1115) id 15O3hoKK023941; Thu, 24 Jun 2021 12:43:50 +0900 X-Iguazu-Qid: 2wGrD5gLVJpuNZD3lg X-Iguazu-QSIG: v=2; s=0; t=1624506230; q=2wGrD5gLVJpuNZD3lg; m=h4DpzGxt0EuktOw7oq1VrB5vUx7smE9ntpLMQ4cDavs= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1113) id 15O3hmeW015679 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Thu, 24 Jun 2021 12:43:49 +0900 Received: from enc01.toshiba.co.jp (enc01.toshiba.co.jp [106.186.93.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by imx2-a.toshiba.co.jp (Postfix) with ESMTPS id 96A0210011D; Thu, 24 Jun 2021 12:43:48 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.toshiba.co.jp with ESMTP id 15O3hlsR008907; Thu, 24 Jun 2021 12:43:48 +0900 From: Nobuhiro Iwamatsu To: Michael Turquette , Stephen Boyd , Rob Herring Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Nobuhiro Iwamatsu Subject: [PATCH v3 3/4] dt-bindings: clock: Add DT bindings for SMU of Toshiba Visconti TMPV770x SoC Date: Thu, 24 Jun 2021 12:43:36 +0900 X-TSB-HOP: ON Message-Id: <20210624034337.282386-4-nobuhiro1.iwamatsu@toshiba.co.jp> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20210624034337.282386-1-nobuhiro1.iwamatsu@toshiba.co.jp> References: <20210624034337.282386-1-nobuhiro1.iwamatsu@toshiba.co.jp> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210623_204359_841263_FCE76C3D X-CRM114-Status: GOOD ( 12.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add device tree bindings for SMU (System Management Unit) controller of Toshiba Visconti TMPV770x SoC series. Signed-off-by: Nobuhiro Iwamatsu --- .../clock/toshiba,tmpv770x-pismu.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml diff --git a/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml new file mode 100644 index 000000000000..18fdf4f2831b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/toshiba,tmpv770x-pismu.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/toshiba,tmpv770x-pismu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti5 TMPV770x SMU controller Device Tree Bindings + +maintainers: + - Nobuhiro Iwamatsu + +description: + Toshia Visconti5 SMU (System Management Unit) which supports the clock + and resets on TMPV770x. + +properties: + compatible: + const: toshiba,tmpv7708-pismu + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pismu: pismu@24200000 { + compatible = "toshiba,tmpv7708-pismu"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +...