diff mbox series

[V5,04/15] ARM: dts: imx6q-dhcom: Adding Wake pin to the PCIe pinctrl

Message ID 20210630121312.87193-4-cniedermaier@dh-electronics.com (mailing list archive)
State New, archived
Headers show
Series [V5,01/15] ARM: dts: imx6q-dhcom: Add the parallel system bus | expand

Commit Message

Christoph Niedermaier June 30, 2021, 12:13 p.m. UTC 
The pin CSI0_DATA_EN is reserved for PCIe Wake. Move this pin to
the SoM devicetree. Add PCIe Reset GPIO to the board devicetree.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Rebase on Shawn Guos branch for-next
V3: - Add Reviewed-by tag
V4: - No changes
V5: - No changes
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts |  7 +++----
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 11 +++++++++++
 2 files changed, 14 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index a685b1c3208f..6c5eaeefa22e 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -232,9 +232,9 @@ 
 		>;
 	};
 
-	pinctrl_pcie: pcie-grp {
+	pinctrl_pcie_reset: pcie-reset-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1
+			MX6QDL_PAD_NANDF_CS1__GPIO6_IO14	0x120b0
 		>;
 	};
 };
@@ -244,8 +244,7 @@ 
 };
 
 &pcie {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_pcie>;
+	pinctrl-0 = <&pinctrl_pcie &pinctrl_pcie_reset>;
 	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index d4a761b6b6aa..c5c060c6b9bf 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -450,6 +450,12 @@ 
 		>;
 	};
 
+	pinctrl_pcie: pcie-grp {
+		fsl,pins = <
+			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
+		>;
+	};
+
 	pinctrl_uart1: uart1-grp {
 		fsl,pins = <
 			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
@@ -568,6 +574,11 @@ 
 	};
 };
 
+&pcie {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie>;
+};
+
 &reg_arm {
 	vin-supply = <&sw3_reg>;
 };