| Message ID | 20210630230129.237658-1-marex@denx.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield | expand |
> Subject: [PATCH 1/2] soc: imx: gpcv2: Turn domain->pgc into bitfield > > There is currently the MX8MM GPU domain, which is in fact a composite > domain for both GPU2D and GPU3D. To correctly configure this domain, it is > necessary to control both GPC_PGC_nCTRL(GPU_2D) and > GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. > > Turn the domain->pgc from value into bitfield and use for_each_set_bit() to > iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL > register array. This way it is possible to configure all GPC_PGC_nCTRL registers > required in a particular domain. > > This is a preparatory patch, no functional change. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Frieder Schrempf <frieder.schrempf@kontron.de> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> > --- > drivers/soc/imx/gpcv2.c | 68 ++++++++++++++++++++++------------------- > 1 file changed, 36 insertions(+), 32 deletions(-) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index > 388c4c729c95b..1cf23144d5378 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -192,7 +192,7 @@ struct imx_pgc_domain { > struct clk_bulk_data *clks; > int num_clks; > > - unsigned int pgc; > + unsigned long pgc; > > const struct { > u32 pxx; > @@ -223,7 +223,7 @@ to_imx_pgc_domain(struct generic_pm_domain > *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd) > { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > ret = pm_runtime_get_sync(domain->dev); @@ -260,8 +260,10 @@ > static int imx_pgc_power_up(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* disable power control */ > - regmap_clear_bits(domain->regmap, > GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power up */ > regmap_update_bits(domain->regmap, > GPC_PU_PGC_SW_PUP_REQ, @@ -330,7 +332,7 @@ static int > imx_pgc_power_up(struct generic_pm_domain *genpd) static int > imx_pgc_power_down(struct generic_pm_domain *genpd) { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > /* Enable reset clocks for all devices in the domain */ @@ -357,8 > +359,10 @@ static int imx_pgc_power_down(struct generic_pm_domain > *genpd) > > if (domain->bits.pxx) { > /* enable power control */ > - regmap_update_bits(domain->regmap, > GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power down */ > regmap_update_bits(domain->regmap, > GPC_PU_PGC_SW_PDN_REQ, @@ -408,7 +412,7 @@ static const struct > imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_MIPI, > + .pgc = BIT(IMX7_PGC_MIPI), > }, > > [IMX7_POWER_DOMAIN_PCIE_PHY] = { > @@ -420,7 +424,7 @@ static const struct imx_pgc_domain > imx7_pgc_domains[] = { > .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_PCIE, > + .pgc = BIT(IMX7_PGC_PCIE), > }, > > [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { > @@ -432,7 +436,7 @@ static const struct imx_pgc_domain > imx7_pgc_domains[] = { > .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, > }, > .voltage = 1200000, > - .pgc = IMX7_PGC_USB_HSIC, > + .pgc = BIT(IMX7_PGC_USB_HSIC), > }, > }; > > @@ -467,7 +471,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_SW_Pxx_REQ, > .map = IMX8M_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI, > + .pgc = BIT(IMX8M_PGC_MIPI), > }, > > [IMX8M_POWER_DOMAIN_PCIE1] = { > @@ -478,7 +482,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE1_SW_Pxx_REQ, > .map = IMX8M_PCIE1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE1, > + .pgc = BIT(IMX8M_PGC_PCIE1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG1] = { > @@ -489,7 +493,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG1_SW_Pxx_REQ, > .map = IMX8M_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG1, > + .pgc = BIT(IMX8M_PGC_OTG1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG2] = { > @@ -500,7 +504,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG2_SW_Pxx_REQ, > .map = IMX8M_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG2, > + .pgc = BIT(IMX8M_PGC_OTG2), > }, > > [IMX8M_POWER_DOMAIN_DDR1] = { > @@ -511,7 +515,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_DDR1_SW_Pxx_REQ, > .map = IMX8M_DDR2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_DDR1, > + .pgc = BIT(IMX8M_PGC_DDR1), > }, > > [IMX8M_POWER_DOMAIN_GPU] = { > @@ -524,7 +528,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .hskreq = IMX8M_GPU_HSK_PWRDNREQN, > .hskack = IMX8M_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_GPU, > + .pgc = BIT(IMX8M_PGC_GPU), > }, > > [IMX8M_POWER_DOMAIN_VPU] = { > @@ -537,7 +541,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .hskreq = IMX8M_VPU_HSK_PWRDNREQN, > .hskack = IMX8M_VPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_VPU, > + .pgc = BIT(IMX8M_PGC_VPU), > }, > > [IMX8M_POWER_DOMAIN_DISP] = { > @@ -550,7 +554,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .hskreq = IMX8M_DISP_HSK_PWRDNREQN, > .hskack = IMX8M_DISP_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_DISP, > + .pgc = BIT(IMX8M_PGC_DISP), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { > @@ -561,7 +565,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI1, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { > @@ -572,7 +576,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI2, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), > }, > > [IMX8M_POWER_DOMAIN_PCIE2] = { > @@ -583,7 +587,7 @@ static const struct imx_pgc_domain > imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE2_SW_Pxx_REQ, > .map = IMX8M_PCIE2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE2, > + .pgc = BIT(IMX8M_PGC_PCIE2), > }, > }; > > @@ -646,7 +650,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_PCIE_SW_Pxx_REQ, > .map = IMX8MM_PCIE_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_PCIE, > + .pgc = BIT(IMX8MM_PGC_PCIE), > }, > > [IMX8MM_POWER_DOMAIN_OTG1] = { > @@ -657,7 +661,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG1_SW_Pxx_REQ, > .map = IMX8MM_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG1, > + .pgc = BIT(IMX8MM_PGC_OTG1), > }, > > [IMX8MM_POWER_DOMAIN_OTG2] = { > @@ -668,7 +672,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG2_SW_Pxx_REQ, > .map = IMX8MM_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG2, > + .pgc = BIT(IMX8MM_PGC_OTG2), > }, > > [IMX8MM_POWER_DOMAIN_GPUMIX] = { > @@ -681,7 +685,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPUMIX, > + .pgc = BIT(IMX8MM_PGC_GPUMIX), > }, > > [IMX8MM_POWER_DOMAIN_GPU] = { > @@ -694,7 +698,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, > .hskack = IMX8MM_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPU2D, > + .pgc = BIT(IMX8MM_PGC_GPU2D), > /* Assert reset, power up domain, deassert reset */ > .reset_assert_early = true, > .reset_deassert_early = false, > @@ -710,7 +714,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_VPUMIX, > + .pgc = BIT(IMX8MM_PGC_VPUMIX), > /* Assert reset, deassert reset, power up domain */ > .reset_assert_early = true, > .reset_deassert_early = true, > @@ -724,7 +728,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, > .map = IMX8MM_VPUG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG1, > + .pgc = BIT(IMX8MM_PGC_VPUG1), > }, > > [IMX8MM_POWER_DOMAIN_VPUG2] = { > @@ -735,7 +739,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, > .map = IMX8MM_VPUG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG2, > + .pgc = BIT(IMX8MM_PGC_VPUG2), > }, > > [IMX8MM_POWER_DOMAIN_VPUH1] = { > @@ -746,7 +750,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, > .map = IMX8MM_VPUH1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUH1, > + .pgc = BIT(IMX8MM_PGC_VPUH1), > }, > > [IMX8MM_POWER_DOMAIN_DISPMIX] = { > @@ -759,7 +763,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_DISPMIX, > + .pgc = BIT(IMX8MM_PGC_DISPMIX), > }, > > [IMX8MM_POWER_DOMAIN_MIPI] = { > @@ -770,7 +774,7 @@ static const struct imx_pgc_domain > imx8mm_pgc_domains[] = { > .pxx = IMX8MM_MIPI_SW_Pxx_REQ, > .map = IMX8MM_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_MIPI, > + .pgc = BIT(IMX8MM_PGC_MIPI), > }, > }; > > -- > 2.30.2
Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut: > There is currently the MX8MM GPU domain, which is in fact a composite domain > for both GPU2D and GPU3D. To correctly configure this domain, it is necessary > to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same > time. This is currently not possible. > > Turn the domain->pgc from value into bitfield and use for_each_set_bit() to > iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL > register array. This way it is possible to configure all GPC_PGC_nCTRL > registers required in a particular domain. > > This is a preparatory patch, no functional change. Which tree was used to generate this patch? This does not apply on top of next or Shawn's imx/drivers tree and from a glance is at least missing the 8MN power domains. Regards, Lucas > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Frieder Schrempf <frieder.schrempf@kontron.de> > Cc: Lucas Stach <l.stach@pengutronix.de> > Cc: NXP Linux Team <linux-imx@nxp.com> > Cc: Peng Fan <peng.fan@nxp.com> > Cc: Shawn Guo <shawnguo@kernel.org> > --- > drivers/soc/imx/gpcv2.c | 68 ++++++++++++++++++++++------------------- > 1 file changed, 36 insertions(+), 32 deletions(-) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index 388c4c729c95b..1cf23144d5378 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -192,7 +192,7 @@ struct imx_pgc_domain { > struct clk_bulk_data *clks; > int num_clks; > > - unsigned int pgc; > + unsigned long pgc; > > const struct { > u32 pxx; > @@ -223,7 +223,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) > static int imx_pgc_power_up(struct generic_pm_domain *genpd) > { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > ret = pm_runtime_get_sync(domain->dev); > @@ -260,8 +260,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* disable power control */ > - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power up */ > regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, > @@ -330,7 +332,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) > static int imx_pgc_power_down(struct generic_pm_domain *genpd) > { > struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); > - u32 reg_val; > + u32 reg_val, pgc; > int ret; > > /* Enable reset clocks for all devices in the domain */ > @@ -357,8 +359,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) > > if (domain->bits.pxx) { > /* enable power control */ > - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), > - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + for_each_set_bit(pgc, &domain->pgc, 32) { > + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), > + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); > + } > > /* request the domain to power down */ > regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, > @@ -408,7 +412,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_MIPI, > + .pgc = BIT(IMX7_PGC_MIPI), > }, > > [IMX7_POWER_DOMAIN_PCIE_PHY] = { > @@ -420,7 +424,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, > }, > .voltage = 1000000, > - .pgc = IMX7_PGC_PCIE, > + .pgc = BIT(IMX7_PGC_PCIE), > }, > > [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { > @@ -432,7 +436,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { > .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, > }, > .voltage = 1200000, > - .pgc = IMX7_PGC_USB_HSIC, > + .pgc = BIT(IMX7_PGC_USB_HSIC), > }, > }; > > @@ -467,7 +471,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_SW_Pxx_REQ, > .map = IMX8M_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI, > + .pgc = BIT(IMX8M_PGC_MIPI), > }, > > [IMX8M_POWER_DOMAIN_PCIE1] = { > @@ -478,7 +482,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE1_SW_Pxx_REQ, > .map = IMX8M_PCIE1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE1, > + .pgc = BIT(IMX8M_PGC_PCIE1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG1] = { > @@ -489,7 +493,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG1_SW_Pxx_REQ, > .map = IMX8M_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG1, > + .pgc = BIT(IMX8M_PGC_OTG1), > }, > > [IMX8M_POWER_DOMAIN_USB_OTG2] = { > @@ -500,7 +504,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_OTG2_SW_Pxx_REQ, > .map = IMX8M_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_OTG2, > + .pgc = BIT(IMX8M_PGC_OTG2), > }, > > [IMX8M_POWER_DOMAIN_DDR1] = { > @@ -511,7 +515,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_DDR1_SW_Pxx_REQ, > .map = IMX8M_DDR2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_DDR1, > + .pgc = BIT(IMX8M_PGC_DDR1), > }, > > [IMX8M_POWER_DOMAIN_GPU] = { > @@ -524,7 +528,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_GPU_HSK_PWRDNREQN, > .hskack = IMX8M_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_GPU, > + .pgc = BIT(IMX8M_PGC_GPU), > }, > > [IMX8M_POWER_DOMAIN_VPU] = { > @@ -537,7 +541,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_VPU_HSK_PWRDNREQN, > .hskack = IMX8M_VPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_VPU, > + .pgc = BIT(IMX8M_PGC_VPU), > }, > > [IMX8M_POWER_DOMAIN_DISP] = { > @@ -550,7 +554,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .hskreq = IMX8M_DISP_HSK_PWRDNREQN, > .hskack = IMX8M_DISP_HSK_PWRDNACKN, > }, > - .pgc = IMX8M_PGC_DISP, > + .pgc = BIT(IMX8M_PGC_DISP), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { > @@ -561,7 +565,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI1_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI1, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), > }, > > [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { > @@ -572,7 +576,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, > .map = IMX8M_MIPI_CSI2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_MIPI_CSI2, > + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), > }, > > [IMX8M_POWER_DOMAIN_PCIE2] = { > @@ -583,7 +587,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { > .pxx = IMX8M_PCIE2_SW_Pxx_REQ, > .map = IMX8M_PCIE2_A53_DOMAIN, > }, > - .pgc = IMX8M_PGC_PCIE2, > + .pgc = BIT(IMX8M_PGC_PCIE2), > }, > }; > > @@ -646,7 +650,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_PCIE_SW_Pxx_REQ, > .map = IMX8MM_PCIE_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_PCIE, > + .pgc = BIT(IMX8MM_PGC_PCIE), > }, > > [IMX8MM_POWER_DOMAIN_OTG1] = { > @@ -657,7 +661,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG1_SW_Pxx_REQ, > .map = IMX8MM_OTG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG1, > + .pgc = BIT(IMX8MM_PGC_OTG1), > }, > > [IMX8MM_POWER_DOMAIN_OTG2] = { > @@ -668,7 +672,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_OTG2_SW_Pxx_REQ, > .map = IMX8MM_OTG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_OTG2, > + .pgc = BIT(IMX8MM_PGC_OTG2), > }, > > [IMX8MM_POWER_DOMAIN_GPUMIX] = { > @@ -681,7 +685,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPUMIX, > + .pgc = BIT(IMX8MM_PGC_GPUMIX), > }, > > [IMX8MM_POWER_DOMAIN_GPU] = { > @@ -694,7 +698,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, > .hskack = IMX8MM_GPU_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_GPU2D, > + .pgc = BIT(IMX8MM_PGC_GPU2D), > /* Assert reset, power up domain, deassert reset */ > .reset_assert_early = true, > .reset_deassert_early = false, > @@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_VPUMIX, > + .pgc = BIT(IMX8MM_PGC_VPUMIX), > /* Assert reset, deassert reset, power up domain */ > .reset_assert_early = true, > .reset_deassert_early = true, > @@ -724,7 +728,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, > .map = IMX8MM_VPUG1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG1, > + .pgc = BIT(IMX8MM_PGC_VPUG1), > }, > > [IMX8MM_POWER_DOMAIN_VPUG2] = { > @@ -735,7 +739,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, > .map = IMX8MM_VPUG2_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUG2, > + .pgc = BIT(IMX8MM_PGC_VPUG2), > }, > > [IMX8MM_POWER_DOMAIN_VPUH1] = { > @@ -746,7 +750,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, > .map = IMX8MM_VPUH1_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_VPUH1, > + .pgc = BIT(IMX8MM_PGC_VPUH1), > }, > > [IMX8MM_POWER_DOMAIN_DISPMIX] = { > @@ -759,7 +763,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, > .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, > }, > - .pgc = IMX8MM_PGC_DISPMIX, > + .pgc = BIT(IMX8MM_PGC_DISPMIX), > }, > > [IMX8MM_POWER_DOMAIN_MIPI] = { > @@ -770,7 +774,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { > .pxx = IMX8MM_MIPI_SW_Pxx_REQ, > .map = IMX8MM_MIPI_A53_DOMAIN, > }, > - .pgc = IMX8MM_PGC_MIPI, > + .pgc = BIT(IMX8MM_PGC_MIPI), > }, > }; >
On 7/2/21 7:02 PM, Lucas Stach wrote: > Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut: >> There is currently the MX8MM GPU domain, which is in fact a composite domain >> for both GPU2D and GPU3D. To correctly configure this domain, it is necessary >> to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same >> time. This is currently not possible. >> >> Turn the domain->pgc from value into bitfield and use for_each_set_bit() to >> iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL >> register array. This way it is possible to configure all GPC_PGC_nCTRL >> registers required in a particular domain. >> >> This is a preparatory patch, no functional change. > > Which tree was used to generate this patch? This does not apply on top > of next or Shawn's imx/drivers tree and from a glance is at least > missing the 8MN power domains. Next with this additional patch [PATCH] soc: imx: gpcv2: Assert reset before ungating clock
Hi Marek, Am Freitag, dem 02.07.2021 um 19:48 +0200 schrieb Marek Vasut: > On 7/2/21 7:02 PM, Lucas Stach wrote: > > Am Donnerstag, dem 01.07.2021 um 01:01 +0200 schrieb Marek Vasut: > > > There is currently the MX8MM GPU domain, which is in fact a composite domain > > > for both GPU2D and GPU3D. To correctly configure this domain, it is necessary > > > to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same > > > time. This is currently not possible. > > > > > > Turn the domain->pgc from value into bitfield and use for_each_set_bit() to > > > iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL > > > register array. This way it is possible to configure all GPC_PGC_nCTRL > > > registers required in a particular domain. > > > > > > This is a preparatory patch, no functional change. > > > > Which tree was used to generate this patch? This does not apply on top > > of next or Shawn's imx/drivers tree and from a glance is at least > > missing the 8MN power domains. > > Next with this additional patch > [PATCH] soc: imx: gpcv2: Assert reset before ungating clock I've picked up this patch in the series of i.MX8MM power domain improvements I just sent. Compared to your version I dropped the above base patch and fixed up the i.MX8MN domains. Regards, Lucas
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 388c4c729c95b..1cf23144d5378 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -192,7 +192,7 @@ struct imx_pgc_domain { struct clk_bulk_data *clks; int num_clks; - unsigned int pgc; + unsigned long pgc; const struct { u32 pxx; @@ -223,7 +223,7 @@ to_imx_pgc_domain(struct generic_pm_domain *genpd) static int imx_pgc_power_up(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; ret = pm_runtime_get_sync(domain->dev); @@ -260,8 +260,10 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* disable power control */ - regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_clear_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR); + } /* request the domain to power up */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ, @@ -330,7 +332,7 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd) static int imx_pgc_power_down(struct generic_pm_domain *genpd) { struct imx_pgc_domain *domain = to_imx_pgc_domain(genpd); - u32 reg_val; + u32 reg_val, pgc; int ret; /* Enable reset clocks for all devices in the domain */ @@ -357,8 +359,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd) if (domain->bits.pxx) { /* enable power control */ - regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc), - GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + for_each_set_bit(pgc, &domain->pgc, 32) { + regmap_update_bits(domain->regmap, GPC_PGC_CTRL(pgc), + GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR); + } /* request the domain to power down */ regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ, @@ -408,7 +412,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_MIPI_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_MIPI, + .pgc = BIT(IMX7_PGC_MIPI), }, [IMX7_POWER_DOMAIN_PCIE_PHY] = { @@ -420,7 +424,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_PCIE_PHY_A_CORE_DOMAIN, }, .voltage = 1000000, - .pgc = IMX7_PGC_PCIE, + .pgc = BIT(IMX7_PGC_PCIE), }, [IMX7_POWER_DOMAIN_USB_HSIC_PHY] = { @@ -432,7 +436,7 @@ static const struct imx_pgc_domain imx7_pgc_domains[] = { .map = IMX7_USB_HSIC_PHY_A_CORE_DOMAIN, }, .voltage = 1200000, - .pgc = IMX7_PGC_USB_HSIC, + .pgc = BIT(IMX7_PGC_USB_HSIC), }, }; @@ -467,7 +471,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_SW_Pxx_REQ, .map = IMX8M_MIPI_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI, + .pgc = BIT(IMX8M_PGC_MIPI), }, [IMX8M_POWER_DOMAIN_PCIE1] = { @@ -478,7 +482,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE1_SW_Pxx_REQ, .map = IMX8M_PCIE1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE1, + .pgc = BIT(IMX8M_PGC_PCIE1), }, [IMX8M_POWER_DOMAIN_USB_OTG1] = { @@ -489,7 +493,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG1_SW_Pxx_REQ, .map = IMX8M_OTG1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG1, + .pgc = BIT(IMX8M_PGC_OTG1), }, [IMX8M_POWER_DOMAIN_USB_OTG2] = { @@ -500,7 +504,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_OTG2_SW_Pxx_REQ, .map = IMX8M_OTG2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_OTG2, + .pgc = BIT(IMX8M_PGC_OTG2), }, [IMX8M_POWER_DOMAIN_DDR1] = { @@ -511,7 +515,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_DDR1_SW_Pxx_REQ, .map = IMX8M_DDR2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_DDR1, + .pgc = BIT(IMX8M_PGC_DDR1), }, [IMX8M_POWER_DOMAIN_GPU] = { @@ -524,7 +528,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_GPU_HSK_PWRDNREQN, .hskack = IMX8M_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_GPU, + .pgc = BIT(IMX8M_PGC_GPU), }, [IMX8M_POWER_DOMAIN_VPU] = { @@ -537,7 +541,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_VPU_HSK_PWRDNREQN, .hskack = IMX8M_VPU_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_VPU, + .pgc = BIT(IMX8M_PGC_VPU), }, [IMX8M_POWER_DOMAIN_DISP] = { @@ -550,7 +554,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .hskreq = IMX8M_DISP_HSK_PWRDNREQN, .hskack = IMX8M_DISP_HSK_PWRDNACKN, }, - .pgc = IMX8M_PGC_DISP, + .pgc = BIT(IMX8M_PGC_DISP), }, [IMX8M_POWER_DOMAIN_MIPI_CSI1] = { @@ -561,7 +565,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI1_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI1_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI1, + .pgc = BIT(IMX8M_PGC_MIPI_CSI1), }, [IMX8M_POWER_DOMAIN_MIPI_CSI2] = { @@ -572,7 +576,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_MIPI_CSI2_SW_Pxx_REQ, .map = IMX8M_MIPI_CSI2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_MIPI_CSI2, + .pgc = BIT(IMX8M_PGC_MIPI_CSI2), }, [IMX8M_POWER_DOMAIN_PCIE2] = { @@ -583,7 +587,7 @@ static const struct imx_pgc_domain imx8m_pgc_domains[] = { .pxx = IMX8M_PCIE2_SW_Pxx_REQ, .map = IMX8M_PCIE2_A53_DOMAIN, }, - .pgc = IMX8M_PGC_PCIE2, + .pgc = BIT(IMX8M_PGC_PCIE2), }, }; @@ -646,7 +650,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_PCIE_SW_Pxx_REQ, .map = IMX8MM_PCIE_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_PCIE, + .pgc = BIT(IMX8MM_PGC_PCIE), }, [IMX8MM_POWER_DOMAIN_OTG1] = { @@ -657,7 +661,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG1_SW_Pxx_REQ, .map = IMX8MM_OTG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG1, + .pgc = BIT(IMX8MM_PGC_OTG1), }, [IMX8MM_POWER_DOMAIN_OTG2] = { @@ -668,7 +672,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_OTG2_SW_Pxx_REQ, .map = IMX8MM_OTG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_OTG2, + .pgc = BIT(IMX8MM_PGC_OTG2), }, [IMX8MM_POWER_DOMAIN_GPUMIX] = { @@ -681,7 +685,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_GPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPUMIX, + .pgc = BIT(IMX8MM_PGC_GPUMIX), }, [IMX8MM_POWER_DOMAIN_GPU] = { @@ -694,7 +698,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_GPU_HSK_PWRDNREQN, .hskack = IMX8MM_GPU_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_GPU2D, + .pgc = BIT(IMX8MM_PGC_GPU2D), /* Assert reset, power up domain, deassert reset */ .reset_assert_early = true, .reset_deassert_early = false, @@ -710,7 +714,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_VPUMIX_HSK_PWRDNREQN, .hskack = IMX8MM_VPUMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_VPUMIX, + .pgc = BIT(IMX8MM_PGC_VPUMIX), /* Assert reset, deassert reset, power up domain */ .reset_assert_early = true, .reset_deassert_early = true, @@ -724,7 +728,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG1_SW_Pxx_REQ, .map = IMX8MM_VPUG1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG1, + .pgc = BIT(IMX8MM_PGC_VPUG1), }, [IMX8MM_POWER_DOMAIN_VPUG2] = { @@ -735,7 +739,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUG2_SW_Pxx_REQ, .map = IMX8MM_VPUG2_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUG2, + .pgc = BIT(IMX8MM_PGC_VPUG2), }, [IMX8MM_POWER_DOMAIN_VPUH1] = { @@ -746,7 +750,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_VPUH1_SW_Pxx_REQ, .map = IMX8MM_VPUH1_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_VPUH1, + .pgc = BIT(IMX8MM_PGC_VPUH1), }, [IMX8MM_POWER_DOMAIN_DISPMIX] = { @@ -759,7 +763,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .hskreq = IMX8MM_DISPMIX_HSK_PWRDNREQN, .hskack = IMX8MM_DISPMIX_HSK_PWRDNACKN, }, - .pgc = IMX8MM_PGC_DISPMIX, + .pgc = BIT(IMX8MM_PGC_DISPMIX), }, [IMX8MM_POWER_DOMAIN_MIPI] = { @@ -770,7 +774,7 @@ static const struct imx_pgc_domain imx8mm_pgc_domains[] = { .pxx = IMX8MM_MIPI_SW_Pxx_REQ, .map = IMX8MM_MIPI_A53_DOMAIN, }, - .pgc = IMX8MM_PGC_MIPI, + .pgc = BIT(IMX8MM_PGC_MIPI), }, };
There is currently the MX8MM GPU domain, which is in fact a composite domain for both GPU2D and GPU3D. To correctly configure this domain, it is necessary to control both GPC_PGC_nCTRL(GPU_2D) and GPC_PGC_nCTRL(GPU_3D) at the same time. This is currently not possible. Turn the domain->pgc from value into bitfield and use for_each_set_bit() to iterate over all bits set in domain->pgc when configuring GPC_PGC_nCTRL register array. This way it is possible to configure all GPC_PGC_nCTRL registers required in a particular domain. This is a preparatory patch, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: NXP Linux Team <linux-imx@nxp.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Shawn Guo <shawnguo@kernel.org> --- drivers/soc/imx/gpcv2.c | 68 ++++++++++++++++++++++------------------- 1 file changed, 36 insertions(+), 32 deletions(-)