@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/mt8195-power.h>
@@ -16,6 +17,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gce0 = &gce0;
+ gce1 = &gce1;
+ };
+
clocks {
clk26m: oscillator0 {
compatible = "fixed-clock";
@@ -717,6 +723,24 @@
#clock-cells = <1>;
};
+ gce0: mdp_mailbox@10320000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <1>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ clock-names = "gce";
+ };
+
+ gce1: disp_mailbox@10330000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <1>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ clock-names = "gce";
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
Add gce node and gce alias on mt8195 dts file. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- This patch is based on [1] [1] Add Mediatek SoC MT8195 and evaluation board dts and Makefile - https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/ --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)