| Message ID | 20210707041249.29816-7-jason-jh.lin@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add MediaTek SoC DRM (vdosys0) support for mt8195 | expand |
Hi, Jason: On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote: > Add mtk-mutex support for mt8195. Separate DRM part and SoC part into different patch. Regards, CK > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + > drivers/soc/mediatek/mtk-mutex.c | 105 +++++++++++++++++++++++-- > 2 files changed, 102 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > index 9074ce32912c..5b7ead493487 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > @@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { > .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = (void *)MTK_DISP_MUTEX }, > + { .compatible = "mediatek,mt8195-disp-mutex", > + .data = (void *)MTK_DISP_MUTEX }, > { .compatible = "mediatek,mt2701-disp-pwm", > .data = (void *)MTK_DISP_BLS }, > { .compatible = "mediatek,mt8173-disp-pwm", > diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c > index 2e4bcc300576..080bdabfb024 100644 > --- a/drivers/soc/mediatek/mtk-mutex.c > +++ b/drivers/soc/mediatek/mtk-mutex.c > @@ -17,6 +17,9 @@ > #define MT8183_MUTEX0_MOD0 0x30 > #define MT8183_MUTEX0_SOF0 0x2c > > +#define MT8195_DISP_MUTEX0_MOD0 0x30 > +#define MT8195_DISP_MUTEX0_SOF 0x2c > + > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) > @@ -67,6 +70,36 @@ > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > #define MT8173_MUTEX_MOD_DISP_OD 25 > > +#define MT8195_MUTEX_MOD_DISP_OVL0 0 > +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 > +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 > +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 > +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 > +#define MT8195_MUTEX_MOD_DISP_AAL0 5 > +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 > +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 > +#define MT8195_MUTEX_MOD_DISP_DSI0 8 > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 > +#define MT8195_MUTEX_MOD_DISP_OVL1 10 > +#define MT8195_MUTEX_MOD_DISP_WDMA1 11 > +#define MT8195_MUTEX_MOD_DISP_RDMA1 12 > +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 > +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 > +#define MT8195_MUTEX_MOD_DISP_AAL1 15 > +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 > +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 > +#define MT8195_MUTEX_MOD_DISP_DSI1 18 > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 > +#define MT8195_MUTEX_MOD_DISP_PWM0 27 > +#define MT8195_MUTEX_MOD_DISP_PWM1 28 > + > #define MT2712_MUTEX_MOD_DISP_PWM2 10 > #define MT2712_MUTEX_MOD_DISP_OVL0 11 > #define MT2712_MUTEX_MOD_DISP_OVL1 12 > @@ -101,11 +134,36 @@ > #define MT2712_MUTEX_SOF_DSI3 6 > #define MT8167_MUTEX_SOF_DPI0 2 > #define MT8167_MUTEX_SOF_DPI1 3 > + > #define MT8183_MUTEX_SOF_DSI0 1 > #define MT8183_MUTEX_SOF_DPI0 2 > > -#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) > -#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) > +#define MT8183_MUTEX_EOF_CONVERT(sof) ((sof) << 6) > +#define MT8183_MUTEX_EOF_DSI0 \ > + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0) > +#define MT8183_MUTEX_EOF_DPI0 \ > + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0) > + > +#define MT8195_MUTEX_SOF_DSI0 1 > +#define MT8195_MUTEX_SOF_DSI1 2 > +#define MT8195_MUTEX_SOF_DP_INTF0 3 > +#define MT8195_MUTEX_SOF_DP_INTF1 4 > +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ > +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ > + > +#define MT8195_MUTEX_EOF_CONVERT(sof) ((sof) << 7) > +#define MT8195_MUTEX_EOF_DSI0 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0) > +#define MT8195_MUTEX_EOF_DSI1 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1) > +#define MT8195_MUTEX_EOF_DP_INTF0 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0) > +#define MT8195_MUTEX_EOF_DP_INTF1 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1) > +#define MT8195_MUTEX_EOF_DPI0 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0) > +#define MT8195_MUTEX_EOF_DPI1 \ > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1) > > struct mtk_mutex { > int id; > @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id { > MUTEX_SOF_DPI1, > MUTEX_SOF_DSI2, > MUTEX_SOF_DSI3, > + MUTEX_SOF_DP_INTF0, > + MUTEX_SOF_DP_INTF1, > + DDP_MUTEX_SOF_MAX, > }; > > struct mtk_mutex_data { > @@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > }; > > -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { > + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, > + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, > + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, > + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, > + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, > + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, > + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, > + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, > + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, > + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, > +}; > + > +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, > @@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > }; > > -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, > @@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > }; > > /* Add EOF setting so overlay hardware can receive frame done irq */ > -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, > }; > > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, > + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, > + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, > + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, > + [MUTEX_SOF_DP_INTF0] = > + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, > + [MUTEX_SOF_DP_INTF1] = > + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, > +}; > + > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > .mutex_mod = mt2701_mutex_mod, > .mutex_sof = mt2712_mutex_sof, > @@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { > .no_clk = true, > }; > > +static const struct mtk_mutex_data mt8195_mutex_driver_data = { > + .mutex_mod = mt8195_mutex_mod, > + .mutex_sof = mt8195_mutex_sof, > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, > +}; > + > struct mtk_mutex *mtk_mutex_get(struct device *dev) > { > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > @@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { > .data = &mt8173_mutex_driver_data}, > { .compatible = "mediatek,mt8183-disp-mutex", > .data = &mt8183_mutex_driver_data}, > + { .compatible = "mediatek,mt8195-disp-mutex", > + .data = &mt8195_mutex_driver_data}, > {}, > }; > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Hi CK, OK, I'll separate DRM part at the next version. Regard, Jason-JH.Lin On Wed, 2021-07-07 at 12:52 +0800, CK Hu wrote: > Hi, Jason: > > On Wed, 2021-07-07 at 12:12 +0800, jason-jh.lin wrote: > > Add mtk-mutex support for mt8195. > > Separate DRM part and SoC part into different patch. > > Regards, > CK > > > > > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + > > drivers/soc/mediatek/mtk-mutex.c | 105 > > +++++++++++++++++++++++-- > > 2 files changed, 102 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > index 9074ce32912c..5b7ead493487 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c > > @@ -470,6 +470,8 @@ static const struct of_device_id > > mtk_ddp_comp_dt_ids[] = { > > .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt8183-disp-mutex", > > .data = (void *)MTK_DISP_MUTEX }, > > + { .compatible = "mediatek,mt8195-disp-mutex", > > + .data = (void *)MTK_DISP_MUTEX }, > > { .compatible = "mediatek,mt2701-disp-pwm", > > .data = (void *)MTK_DISP_BLS }, > > { .compatible = "mediatek,mt8173-disp-pwm", > > diff --git a/drivers/soc/mediatek/mtk-mutex.c > > b/drivers/soc/mediatek/mtk-mutex.c > > index 2e4bcc300576..080bdabfb024 100644 > > --- a/drivers/soc/mediatek/mtk-mutex.c > > +++ b/drivers/soc/mediatek/mtk-mutex.c > > @@ -17,6 +17,9 @@ > > #define MT8183_MUTEX0_MOD0 0x30 > > #define MT8183_MUTEX0_SOF0 0x2c > > > > +#define MT8195_DISP_MUTEX0_MOD0 0x30 > > +#define MT8195_DISP_MUTEX0_SOF 0x2c > > + > > #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * > > (n)) > > #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) > > #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * > > (n)) > > @@ -67,6 +70,36 @@ > > #define MT8173_MUTEX_MOD_DISP_PWM1 24 > > #define MT8173_MUTEX_MOD_DISP_OD 25 > > > > +#define MT8195_MUTEX_MOD_DISP_OVL0 0 > > +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 > > +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 > > +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 > > +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 > > +#define MT8195_MUTEX_MOD_DISP_AAL0 5 > > +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 > > +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 > > +#define MT8195_MUTEX_MOD_DISP_DSI0 8 > > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 > > +#define MT8195_MUTEX_MOD_DISP_OVL1 10 > > +#define MT8195_MUTEX_MOD_DISP_WDMA1 11 > > +#define MT8195_MUTEX_MOD_DISP_RDMA1 12 > > +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 > > +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 > > +#define MT8195_MUTEX_MOD_DISP_AAL1 15 > > +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 > > +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 > > +#define MT8195_MUTEX_MOD_DISP_DSI1 18 > > +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 > > +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 > > +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 > > +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 > > +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 > > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 > > +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 > > +#define MT8195_MUTEX_MOD_DISP_PWM0 27 > > +#define MT8195_MUTEX_MOD_DISP_PWM1 28 > > + > > #define MT2712_MUTEX_MOD_DISP_PWM2 10 > > #define MT2712_MUTEX_MOD_DISP_OVL0 11 > > #define MT2712_MUTEX_MOD_DISP_OVL1 12 > > @@ -101,11 +134,36 @@ > > #define MT2712_MUTEX_SOF_DSI3 6 > > #define MT8167_MUTEX_SOF_DPI0 2 > > #define MT8167_MUTEX_SOF_DPI1 3 > > + > > #define MT8183_MUTEX_SOF_DSI0 1 > > #define MT8183_MUTEX_SOF_DPI0 2 > > > > -#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S > > OF_DSI0 << 6) > > -#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S > > OF_DPI0 << 6) > > +#define MT8183_MUTEX_EOF_CONVERT(sof) ((sof) << 6) > > +#define MT8183_MUTEX_EOF_DSI0 \ > > + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0) > > +#define MT8183_MUTEX_EOF_DPI0 \ > > + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0) > > + > > +#define MT8195_MUTEX_SOF_DSI0 1 > > +#define MT8195_MUTEX_SOF_DSI1 2 > > +#define MT8195_MUTEX_SOF_DP_INTF0 3 > > +#define MT8195_MUTEX_SOF_DP_INTF1 4 > > +#define MT8195_MUTEX_SOF_DPI0 6 /* for > > HDMI_TX */ > > +#define MT8195_MUTEX_SOF_DPI1 5 /* for > > digital video out */ > > + > > +#define MT8195_MUTEX_EOF_CONVERT(sof) ((sof) << 7) > > +#define MT8195_MUTEX_EOF_DSI0 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0) > > +#define MT8195_MUTEX_EOF_DSI1 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1) > > +#define MT8195_MUTEX_EOF_DP_INTF0 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0) > > +#define MT8195_MUTEX_EOF_DP_INTF1 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1) > > +#define MT8195_MUTEX_EOF_DPI0 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0) > > +#define MT8195_MUTEX_EOF_DPI1 \ > > + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1) > > > > struct mtk_mutex { > > int id; > > @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id { > > MUTEX_SOF_DPI1, > > MUTEX_SOF_DSI2, > > MUTEX_SOF_DSI3, > > + MUTEX_SOF_DP_INTF0, > > + MUTEX_SOF_DP_INTF1, > > + DDP_MUTEX_SOF_MAX, > > }; > > > > struct mtk_mutex_data { > > @@ -214,7 +275,20 @@ static const unsigned int > > mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { > > [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, > > }; > > > > -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = > > { > > + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, > > + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, > > + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, > > + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, > > + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, > > + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, > > + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, > > + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, > > + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, > > + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, > > +}; > > + > > +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, > > @@ -224,7 +298,7 @@ static const unsigned int > > mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, > > }; > > > > -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, > > [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, > > @@ -232,12 +306,24 @@ static const unsigned int > > mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > }; > > > > /* Add EOF setting so overlay hardware can receive frame done irq > > */ > > -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { > > +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, > > [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | > > MT8183_MUTEX_EOF_DPI0, > > }; > > > > +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { > > + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, > > + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | > > MT8195_MUTEX_EOF_DSI0, > > + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | > > MT8195_MUTEX_EOF_DSI1, > > + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | > > MT8195_MUTEX_EOF_DPI0, > > + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | > > MT8195_MUTEX_EOF_DPI1, > > + [MUTEX_SOF_DP_INTF0] = > > + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, > > + [MUTEX_SOF_DP_INTF1] = > > + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, > > +}; > > + > > static const struct mtk_mutex_data mt2701_mutex_driver_data = { > > .mutex_mod = mt2701_mutex_mod, > > .mutex_sof = mt2712_mutex_sof, > > @@ -275,6 +361,13 @@ static const struct mtk_mutex_data > > mt8183_mutex_driver_data = { > > .no_clk = true, > > }; > > > > +static const struct mtk_mutex_data mt8195_mutex_driver_data = { > > + .mutex_mod = mt8195_mutex_mod, > > + .mutex_sof = mt8195_mutex_sof, > > + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, > > + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, > > +}; > > + > > struct mtk_mutex *mtk_mutex_get(struct device *dev) > > { > > struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); > > @@ -507,6 +600,8 @@ static const struct of_device_id > > mutex_driver_dt_match[] = { > > .data = &mt8173_mutex_driver_data}, > > { .compatible = "mediatek,mt8183-disp-mutex", > > .data = &mt8183_mutex_driver_data}, > > + { .compatible = "mediatek,mt8195-disp-mutex", > > + .data = &mt8195_mutex_driver_data}, > > {}, > > }; > > MODULE_DEVICE_TABLE(of, mutex_driver_dt_match); > >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c index 9074ce32912c..5b7ead493487 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -470,6 +470,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = { .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt8183-disp-mutex", .data = (void *)MTK_DISP_MUTEX }, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = (void *)MTK_DISP_MUTEX }, { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS }, { .compatible = "mediatek,mt8173-disp-pwm", diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2e4bcc300576..080bdabfb024 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -17,6 +17,9 @@ #define MT8183_MUTEX0_MOD0 0x30 #define MT8183_MUTEX0_SOF0 0x2c +#define MT8195_DISP_MUTEX0_MOD0 0x30 +#define MT8195_DISP_MUTEX0_SOF 0x2c + #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) @@ -67,6 +70,36 @@ #define MT8173_MUTEX_MOD_DISP_PWM1 24 #define MT8173_MUTEX_MOD_DISP_OD 25 +#define MT8195_MUTEX_MOD_DISP_OVL0 0 +#define MT8195_MUTEX_MOD_DISP_WDMA0 1 +#define MT8195_MUTEX_MOD_DISP_RDMA0 2 +#define MT8195_MUTEX_MOD_DISP_COLOR0 3 +#define MT8195_MUTEX_MOD_DISP_CCORR0 4 +#define MT8195_MUTEX_MOD_DISP_AAL0 5 +#define MT8195_MUTEX_MOD_DISP_GAMMA0 6 +#define MT8195_MUTEX_MOD_DISP_DITHER0 7 +#define MT8195_MUTEX_MOD_DISP_DSI0 8 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9 +#define MT8195_MUTEX_MOD_DISP_OVL1 10 +#define MT8195_MUTEX_MOD_DISP_WDMA1 11 +#define MT8195_MUTEX_MOD_DISP_RDMA1 12 +#define MT8195_MUTEX_MOD_DISP_COLOR1 13 +#define MT8195_MUTEX_MOD_DISP_CCORR1 14 +#define MT8195_MUTEX_MOD_DISP_AAL1 15 +#define MT8195_MUTEX_MOD_DISP_GAMMA1 16 +#define MT8195_MUTEX_MOD_DISP_DITHER1 17 +#define MT8195_MUTEX_MOD_DISP_DSI1 18 +#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19 +#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20 +#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22 +#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23 +#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25 +#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26 +#define MT8195_MUTEX_MOD_DISP_PWM0 27 +#define MT8195_MUTEX_MOD_DISP_PWM1 28 + #define MT2712_MUTEX_MOD_DISP_PWM2 10 #define MT2712_MUTEX_MOD_DISP_OVL0 11 #define MT2712_MUTEX_MOD_DISP_OVL1 12 @@ -101,11 +134,36 @@ #define MT2712_MUTEX_SOF_DSI3 6 #define MT8167_MUTEX_SOF_DPI0 2 #define MT8167_MUTEX_SOF_DPI1 3 + #define MT8183_MUTEX_SOF_DSI0 1 #define MT8183_MUTEX_SOF_DPI0 2 -#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) -#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8183_MUTEX_EOF_CONVERT(sof) ((sof) << 6) +#define MT8183_MUTEX_EOF_DSI0 \ + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DSI0) +#define MT8183_MUTEX_EOF_DPI0 \ + MT8183_MUTEX_EOF_CONVERT(MT8183_MUTEX_SOF_DPI0) + +#define MT8195_MUTEX_SOF_DSI0 1 +#define MT8195_MUTEX_SOF_DSI1 2 +#define MT8195_MUTEX_SOF_DP_INTF0 3 +#define MT8195_MUTEX_SOF_DP_INTF1 4 +#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */ +#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */ + +#define MT8195_MUTEX_EOF_CONVERT(sof) ((sof) << 7) +#define MT8195_MUTEX_EOF_DSI0 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI0) +#define MT8195_MUTEX_EOF_DSI1 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DSI1) +#define MT8195_MUTEX_EOF_DP_INTF0 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF0) +#define MT8195_MUTEX_EOF_DP_INTF1 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DP_INTF1) +#define MT8195_MUTEX_EOF_DPI0 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI0) +#define MT8195_MUTEX_EOF_DPI1 \ + MT8195_MUTEX_EOF_CONVERT(MT8195_MUTEX_SOF_DPI1) struct mtk_mutex { int id; @@ -120,6 +178,9 @@ enum mtk_mutex_sof_id { MUTEX_SOF_DPI1, MUTEX_SOF_DSI2, MUTEX_SOF_DSI3, + MUTEX_SOF_DP_INTF0, + MUTEX_SOF_DP_INTF1, + DDP_MUTEX_SOF_MAX, }; struct mtk_mutex_data { @@ -214,7 +275,20 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0, }; -static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = { + [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0, + [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0, + [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0, + [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0, + [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0, + [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0, + [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0, + [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0, + [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0, + [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0, +}; + +static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, @@ -224,7 +298,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3, }; -static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0, @@ -232,12 +306,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = { }; /* Add EOF setting so overlay hardware can receive frame done irq */ -static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = { [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0, [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, }; +static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = { + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, + [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0, + [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1, + [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0, + [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1, + [MUTEX_SOF_DP_INTF0] = + MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0, + [MUTEX_SOF_DP_INTF1] = + MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1, +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -275,6 +361,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .no_clk = true, }; +static const struct mtk_mutex_data mt8195_mutex_driver_data = { + .mutex_mod = mt8195_mutex_mod, + .mutex_sof = mt8195_mutex_sof, + .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0, + .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF, +}; + struct mtk_mutex *mtk_mutex_get(struct device *dev) { struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); @@ -507,6 +600,8 @@ static const struct of_device_id mutex_driver_dt_match[] = { .data = &mt8173_mutex_driver_data}, { .compatible = "mediatek,mt8183-disp-mutex", .data = &mt8183_mutex_driver_data}, + { .compatible = "mediatek,mt8195-disp-mutex", + .data = &mt8195_mutex_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
Add mtk-mutex support for mt8195. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 + drivers/soc/mediatek/mtk-mutex.c | 105 +++++++++++++++++++++++-- 2 files changed, 102 insertions(+), 5 deletions(-)