From patchwork Tue Jul 13 02:05:52 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YT Lee X-Patchwork-Id: 12372693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.4 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78494C07E9A for ; Tue, 13 Jul 2021 02:07:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 44C9061002 for ; Tue, 13 Jul 2021 02:07:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 44C9061002 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yQBhFPOZCMxbvG7WJNys2uUlcl0WyA2L0RGoA8my/yg=; b=L5v0cqXwAvLrNF MpDXxNe4dX/YixEVw7FYy7IV3TRbLFX+S8TTfOEGpappMJ9C1T7pgvFqPN9D40EB14r4MFjb4Dkzo alTHiZa88AIO7DtDfShP2xBVfzEzCNMFlmg11Pkf/CPQ/hXKkNC/BXIz9IRsKM7YdccqEu9UOdGvF FCY4lq/Nfwh758/SeHyO1PyhQHuuuQHKZlZZ2VTObhSQv8x0sKlp5N0o8CmffvpgTP5xgnJPXjir7 OsdfZ3gs3o+JJr0Lr4JtZBzmVsSp4yUtRQWeTRrIjhFrF+jimz967JP5HERHlsn9+BCBpn/WDkHaA TmvwxBEMevFcagH7jF+Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1m37oP-008u9O-Am; Tue, 13 Jul 2021 02:06:17 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1m37oJ-008u7V-TQ; Tue, 13 Jul 2021 02:06:13 +0000 X-UUID: 2f7011d53f034a31b0882a36dd013717-20210712 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=OCMWEVea1jywk8a7q//R87FSsrnN5TPM+Xw3jKcdtfQ=; b=jILvohF494kvrWMAkMNhdveIag/xIcOWbn9GQvoZZy9wUiwxseMBCVVWVzeVHIHLXV7uqbdVuebBiOIDiAVW7thgLUqCTfCv++zwIRVcinPBx9Ncqe5h8kNSVJqxEMCkbP6kb5a/aXIqSyQ/HXtzkb1w7Oe9mVCPddEBpSnAO24=; X-UUID: 2f7011d53f034a31b0882a36dd013717-20210712 Received: from mtkcas67.mediatek.inc [(172.29.193.45)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1981680639; Mon, 12 Jul 2021 19:06:04 -0700 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by MTKMBS62N2.mediatek.inc (172.29.193.42) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Jul 2021 19:06:02 -0700 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Jul 2021 10:06:00 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 13 Jul 2021 10:06:00 +0800 From: YT Lee To: , , , , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH 2/2] soc: mediatek: SVS: add mt8195 SVS GPU driver Date: Tue, 13 Jul 2021 10:05:52 +0800 Message-ID: <20210713020552.18667-3-yt.lee@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210713020552.18667-1-yt.lee@mediatek.com> References: <20210713020552.18667-1-yt.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210712_190612_015007_53E0B658 X-CRM114-Status: GOOD ( 18.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To support SVS GPU on mt8195, add corresponding bank information, platform data and parsing function. Signed-off-by: YT Lee --- This patch depends on "soc: mediatek: SVS: introduce MTK SVS"[1], also refine svs_suspend, svs_resume functions according to [2]. [1]http://lists.infradead.org/pipermail/linux-mediatek/2021-July/026270.html [2]http://lists.infradead.org/pipermail/linux-mediatek/2021-July/026282.html drivers/soc/mediatek/mtk-svs.c | 228 +++++++++++++++++++++++++++++++-- 1 file changed, 216 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mtk-svs.c b/drivers/soc/mediatek/mtk-svs.c index 67f1ea23ea0a..2a07d79d24cb 100644 --- a/drivers/soc/mediatek/mtk-svs.c +++ b/drivers/soc/mediatek/mtk-svs.c @@ -1440,6 +1440,88 @@ static int svs_resource_setup(struct svs_platform *svsp) return 0; } +static bool svs_mt8195_efuse_parsing(struct svs_platform *svsp) +{ + struct svs_bank *svsb; + struct nvmem_cell *cell; + u32 idx, i, ft_pgm, vmin, golden_temp; + + for (i = 0; i < svsp->efuse_num; i++) + if (svsp->efuse[i]) + dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n", + i, svsp->efuse[i]); + + /* Svs efuse parsing */ + ft_pgm = svsp->efuse[0] & GENMASK(7, 0); + vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0); + + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + + if (svsb->sw_id != SVSB_GPU) + return false; + + if (vmin == 0x1) + svsb->vmin = 0x1e; + + if (ft_pgm == 0) + svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE; + + if (svsb->type == SVSB_LOW) { + svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + svsb->vmax += svsb->dvt_fixed; + } else if (svsb->type == SVSB_HIGH) { + svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0); + svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0); + svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0); + svsb->dcbdet = (svsp->efuse[8]) & GENMASK(7, 0); + svsb->dcmdet = (svsp->efuse[8] >> 8) & GENMASK(7, 0); + svsb->vmax += svsb->dvt_fixed; + } + } + + /* Thermal efuse parsing */ + cell = nvmem_cell_get(svsp->dev, "t-calibration-data"); + if (IS_ERR_OR_NULL(cell)) { + dev_err(svsp->dev, "no thermal cell, no mon mode\n"); + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + svsb->mode_support &= ~SVSB_MODE_MON; + } + + return true; + } + + svsp->tefuse = nvmem_cell_read(cell, &svsp->tefuse_num); + svsp->tefuse_num /= sizeof(u32); + nvmem_cell_put(cell); + + for (i = 0; i < svsp->tefuse_num; i++) + if (svsp->tefuse[i] != 0) + break; + + if (i == svsp->tefuse_num) + golden_temp = 50; /* All thermal efuse data are 0 */ + else + golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0); + + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + + if (svsb->sw_id != SVSB_GPU) + return false; + + svsb->mts = 500; + svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4; + } + + return true; +} + static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp) { struct svs_bank *svsb; @@ -1771,12 +1853,10 @@ static int svs_suspend(struct device *dev) } } - if (svsp->rst) { - ret = reset_control_assert(svsp->rst); - if (ret) { - dev_err(svsp->dev, "cannot assert reset %d\n", ret); - return ret; - } + ret = reset_control_assert(svsp->rst); + if (ret) { + dev_err(svsp->dev, "cannot assert reset %d\n", ret); + return ret; } clk_disable_unprepare(svsp->main_clk); @@ -1797,12 +1877,10 @@ static int svs_resume(struct device *dev) return ret; } - if (svsp->rst) { - ret = reset_control_deassert(svsp->rst); - if (ret) { - dev_err(svsp->dev, "cannot deassert reset %d\n", ret); - return ret; - } + ret = reset_control_deassert(svsp->rst); + if (ret) { + dev_err(svsp->dev, "cannot deassert reset %d\n", ret); + return ret; } for (idx = 0; idx < svsp->bank_num; idx++) { @@ -2081,6 +2159,89 @@ static int svs_create_svs_debug_cmds(struct svs_platform *svsp) return 0; } +static struct svs_bank svs_mt8195_banks[] = { + { + .sw_id = SVSB_GPU, + .set_freqs_pct = svs_set_freqs_pct_v3, + .get_vops = svs_get_vops_v3, + .hw_id = 0, + .tzone_name = "gpu1", + .buck_name = "mali", + .volt_flags = SVSB_INIT02_RM_DVTFIXED | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02, + .opp_count = 16, + .freq_base = 640000000, + .turn_freq_base = 640000000, + .vboot = 0x38, + .volt_step = 6250, + .volt_base = 400000, + .volt_offset = 0, + .vmax = 0x38, + .vmin = 0x14, + .dthi = 0x1, + .dtlo = 0xfe, + .det_window = 0xa28, + .det_max = 0xffff, + .age_config = 0x555555, + .agem = 0, + .dc_config = 0x1, + .dvt_fixed = 0x1, + .vco = 0x18, + .chk_shift = 0x87, + .temp_upper_bound = 0x64, + .temp_lower_bound = 0xb2, + .tzone_high_temp = 85000, + .tzone_high_temp_offset = 0, + .tzone_low_temp = 25000, + .tzone_low_temp_offset = 7, + .core_sel = 0x0fff0100, + .int_st = BIT(0), + .ctl0 = 0x00540003, + .type = SVSB_LOW, + }, + { + .sw_id = SVSB_GPU, + .set_freqs_pct = svs_set_freqs_pct_v3, + .get_vops = svs_get_vops_v3, + .hw_id = 1, + .tzone_name = "gpu1", + .buck_name = "mali", + .volt_flags = SVSB_INIT02_RM_DVTFIXED | + SVSB_MON_VOLT_IGNORE, + .mode_support = SVSB_MODE_INIT02 | SVSB_MODE_MON, + .opp_count = 16, + .freq_base = 880000000, + .turn_freq_base = 640000000, + .vboot = 0x38, + .volt_step = 6250, + .volt_base = 400000, + .volt_offset = 0, + .vmax = 0x38, + .vmin = 0x14, + .dthi = 0x1, + .dtlo = 0xfe, + .det_window = 0xa28, + .det_max = 0xffff, + .age_config = 0x555555, + .agem = 0, + .dc_config = 0x1, + .dvt_fixed = 0x6, + .vco = 0x18, + .chk_shift = 0x87, + .temp_upper_bound = 0x64, + .temp_lower_bound = 0xb2, + .tzone_high_temp = 85000, + .tzone_high_temp_offset = 0, + .tzone_low_temp = 25000, + .tzone_low_temp_offset = 7, + .core_sel = 0x0fff0101, + .int_st = BIT(1), + .ctl0 = 0x00540003, + .type = SVSB_HIGH, + }, +}; + static struct svs_bank svs_mt8192_banks[] = { { .sw_id = SVSB_GPU, @@ -2318,6 +2479,46 @@ static struct svs_bank svs_mt8183_banks[] = { }, }; +static int svs_get_svs_mt8195_platform_data(struct svs_platform *svsp) +{ + struct device *dev; + struct svs_bank *svsb; + u32 idx; + + svsp->name = "mt8195-svs"; + svsp->banks = svs_mt8195_banks; + svsp->efuse_parsing = svs_mt8195_efuse_parsing; + svsp->regs = svs_regs_v2; + svsp->irqflags = IRQF_TRIGGER_HIGH; + svsp->bank_num = ARRAY_SIZE(svs_mt8195_banks); + svsp->efuse_check = 10; + + svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst"); + if (IS_ERR(svsp->rst)) { + dev_err_probe(svsp->dev, PTR_ERR(svsp->rst), + "cannot get svs reset control\n"); + return PTR_ERR(svsp->rst); + } + + dev = svs_add_device_link(svsp, "lvts"); + if (IS_ERR(dev)) + return PTR_ERR(dev); + + for (idx = 0; idx < svsp->bank_num; idx++) { + svsb = &svsp->banks[idx]; + + if (svsb->type == SVSB_HIGH) + svsb->opp_dev = svs_add_device_link(svsp, "mali"); + else if (svsb->type == SVSB_LOW) + svsb->opp_dev = svs_get_subsys_device(svsp, "mali"); + + if (IS_ERR(svsb->opp_dev)) + return PTR_ERR(svsb->opp_dev); + } + + return 0; +} + static int svs_get_svs_mt8192_platform_data(struct svs_platform *svsp) { struct device *dev; @@ -2414,6 +2615,9 @@ static const struct of_device_id mtk_svs_of_match[] = { }, { .compatible = "mediatek,mt8192-svs", .data = &svs_get_svs_mt8192_platform_data, + }, { + .compatible = "mediatek,mt8195-svs", + .data = &svs_get_svs_mt8195_platform_data, }, { /* Sentinel */ },