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Wed, 14 Jul 2021 23:09:12 +0200 Received: from localhost.localdomain (172.16.51.7) by DHPWEX01.DH-ELECTRONICS.ORG (10.64.2.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.858.12 via Frontend Transport; Wed, 14 Jul 2021 23:09:12 +0200 From: Christoph Niedermaier To: CC: Christoph Niedermaier , Shawn Guo , Fabio Estevam , Marek Vasut , NXP Linux Team , Subject: [PATCH V6 02/15] ARM: dts: imx6q-dhcom: Add interrupt and compatible to the ethernet PHY Date: Wed, 14 Jul 2021 23:07:00 +0200 Message-ID: <20210714210713.9015-2-cniedermaier@dh-electronics.com> X-Mailer: git-send-email 2.11.0 X-klartext: yes In-Reply-To: <20210714210713.9015-1-cniedermaier@dh-electronics.com> References: <20210714210713.9015-1-cniedermaier@dh-electronics.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210714_140956_735743_AA202711 X-CRM114-Status: GOOD ( 14.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable the interrupt mode for the ethernet PHY by adding the necessary property and a separate pinctrl for the PHY. Also add the compatible property for it. Signed-off-by: Christoph Niedermaier Reviewed-by: Marek Vasut Cc: Shawn Guo Cc: Fabio Estevam Cc: Marek Vasut Cc: NXP Linux Team Cc: kernel@dh-electronics.com To: linux-arm-kernel@lists.infradead.org --- V2: - Rebase on Shawn Guos branch for-next V3: - Add Reviewed-by tag V4: - No changes V5: - No changes V6: - Rebase on 5.14-rc1 --- arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi index 921a695b79fb..0b318d42fe71 100644 --- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi +++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi @@ -124,8 +124,13 @@ #size-cells = <0>; ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */ - reg = <0>; + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; max-speed = <100>; + pinctrl-0 = <&pinctrl_ethphy0>; + pinctrl-names = "default"; + reg = <0>; reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; @@ -299,8 +304,6 @@ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x000b0 - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b1 >; }; @@ -310,6 +313,13 @@ >; }; + pinctrl_ethphy0: ethphy0-grp { + fsl,pins = < + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0 /* Reset */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0xb1 /* Int */ + >; + }; + pinctrl_flexcan1: flexcan1-grp { fsl,pins = < MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0