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[1/6] dt-bindings: imx6q-pcie: add compatible for IMX8MM support

Message ID 20210723204958.7186-2-tharvey@gateworks.com (mailing list archive)
State New, archived
Headers show
Series Add IMX8M Mini PCI support | expand

Commit Message

Tim Harvey July 23, 2021, 8:49 p.m. UTC
This adds the DT binding for IMX8MM support to the existing imx6q-pcie
driver which shares most functionality with the IMX8MM.

Additionally a 'fsl,ext-osc' property is defined to note use of an
external oscillator as ref clock vs the internal PLL.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index d8971ab99274..9886e1344fd3 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -10,6 +10,7 @@  Required properties:
 	- "fsl,imx6qp-pcie"
 	- "fsl,imx7d-pcie"
 	- "fsl,imx8mq-pcie"
+	- "fsl,imx8mm-pcie"
 - reg: base address and length of the PCIe controller
 - interrupts: A list of interrupt outputs of the controller. Must contain an
   entry for each entry in the interrupt-names property.
@@ -19,6 +20,7 @@  Required properties:
 	- "pcie_phy"
 Optional properties:
+- fsl,ext-osc: use the external oscillator as ref clock (vs internal PLL)
 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
 - fsl,tx-deemph-gen2-6db: Gen2 (6db) De-emphasis value. Default: 20
@@ -49,7 +51,7 @@  Additional required properties for imx6sx-pcie:
   PCIE_PHY power domains
 - power-domain-names: Must be "pcie", "pcie_phy"
-Additional required properties for imx7d-pcie and imx8mq-pcie:
+Additional required properties for imx7d-pcie, imx8mq-pcie, imx8mm-pcie:
 - power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
 - resets: Must contain phandles to PCIe-related reset lines exposed by SRC
   IP block