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IronPort-SDR: EbLnsmlB66hSQJ1YjCE/c1GNhGfiipcd1EfNwGPHWZ29bgrj8OhYM5oju0bjJOOJ0B6nvBHv3J Fcv1QFZntOYX5gSoRN8ZO4pY9MR259PGm23Rihe+Ev5D54sgMYnnrZXDB5PmxhXSBTQq3oDeUC cnD4Wka3j+JY4AWuZhaeh7ZCxvcvdtxxT1ceuuWrjO6alEx3DKk0GGC6JObvR3WN+bOmprz2Uh lxxyt6M1FelqQ3IZLexaEMAv2XkdMi4OSuLJzl0Y3oWlYan7oGzLa2Mx2xy2nQkyer0mGEzWip i/5+8oZIy2a/5hZ3I2aThKyK X-IronPort-AV: E=Sophos;i="5.84,272,1620716400"; d="scan'208";a="123560027" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 26 Jul 2021 21:54:06 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 26 Jul 2021 21:54:06 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Mon, 26 Jul 2021 21:54:01 -0700 From: Tudor Ambarus To: , , Subject: [PATCH v2 19/35] mtd: spi-nor: Get rid of SPI_NOR_IO_MODE_EN_VOLATILE flag Date: Tue, 27 Jul 2021 07:52:06 +0300 Message-ID: <20210727045222.905056-20-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210727045222.905056-1-tudor.ambarus@microchip.com> References: <20210727045222.905056-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210726_215407_630116_36807BC4 X-CRM114-Status: GOOD ( 13.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: macromorgan@hotmail.com, jaimeliao@mxic.com.tw, Tudor Ambarus , richard@nod.at, esben@geanix.com, linux@rasmusvillemoes.dk, knaerzche@gmail.com, linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org, code@reto-schneider.ch, miquel.raynal@bootlin.com, heiko.thiery@gmail.com, sr@denx.de, figgyc@figgyc.uk, mail@david-bauer.net, zhengxunli@mxic.com.tw Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Get rid of flash_info flags that indicate settings which can be discovered when parsing SFDP. It will be clearer who sets what, and we'll restrict the flash settings that a developer can choose to only settings that are not SFDP discoverable. SNOR_F_IO_MODE_EN_VOLATILE is discoverable when parsing the optional SCCR Map SFDP table. Flashes that do not define this table should set the flag in the late_init() call. Flashes that define the SFDP optional table but get the value wrong, should fix it in a post_sfdp fixup hook. Signed-off-by: Tudor Ambarus --- drivers/mtd/spi-nor/core.c | 3 --- drivers/mtd/spi-nor/core.h | 9 ++------- drivers/mtd/spi-nor/micron-st.c | 11 ++++++++--- 3 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 240d5c31af88..9885d434ea83 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3204,9 +3204,6 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, if (ret) return ret; - if (info->flags & SPI_NOR_IO_MODE_EN_VOLATILE) - nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; - ret = spi_nor_set_addr_width(nor); if (ret) return ret; diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index dfdc51a26cad..987797a789c8 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -367,17 +367,12 @@ struct flash_info { */ #define SPI_NOR_OCTAL_DTR_READ BIT(18) /* Flash supports octal DTR Read. */ #define SPI_NOR_OCTAL_DTR_PP BIT(19) /* Flash supports Octal DTR Page Program */ -#define SPI_NOR_IO_MODE_EN_VOLATILE BIT(20) /* - * Flash enables the best - * available I/O mode via a - * volatile bit. - */ -#define SPI_NOR_SWP_IS_VOLATILE BIT(21) /* +#define SPI_NOR_SWP_IS_VOLATILE BIT(20) /* * Flash has volatile software write * protection bits. Usually these will * power-up in a write-protected state. */ -#define SPI_NOR_PARSE_SFDP BIT(22) /* +#define SPI_NOR_PARSE_SFDP BIT(21) /* * Flash initialized based on the SFDP * tables. */ diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c index 72cc4673bf88..31ebd4c9b431 100644 --- a/drivers/mtd/spi-nor/micron-st.c +++ b/drivers/mtd/spi-nor/micron-st.c @@ -118,13 +118,18 @@ static struct spi_nor_fixups mt35xu512aba_fixups = { .post_sfdp = mt35xu512aba_post_sfdp_fixup, }; +static void mt35xu512aba_late_init(struct spi_nor *nor) +{ + nor->flags |= SNOR_F_4B_OPCODES; + nor->flags |= SNOR_F_IO_MODE_EN_VOLATILE; +} + static const struct flash_info micron_parts[] = { { "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | - SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP | - SPI_NOR_IO_MODE_EN_VOLATILE) + SPI_NOR_OCTAL_DTR_READ | SPI_NOR_OCTAL_DTR_PP) .fixups = &mt35xu512aba_fixups, - .late_init = snor_f_4b_opcodes, }, + .late_init = mt35xu512aba_late_init, }, { "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ) .late_init = snor_f_4b_opcodes, },