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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=/IaHSSlN75Z3dJZ9FM88aNBUpjs0AGlmoJH6rSKsG9o=; b=mfm/cNoGDazov0tb2i9ezUqYh/sm8k2/NORPx5w6WR1P7NoCy93viPVLXx7WNuDHY+ QirLuO+GYb+x4s7GMq3gc/WRnRmEGHYCMga0Q9GeXCEKEB7DlB16paIj0xn5PVWlUc0f VPfK+iCULSI0gzfQmIntxck6/YE2oLlvGl3wBVyisSgviFZQuJR4mKKE8CNtg0R4E8fT OhKyHf+o4iyQWh+mNhJLswNdaACTaYOT6xhxver0FUjji2KmcSEcm9ajciwHjmhHhNmn 59ry+kWcRfn0dDyxsLa+ZfeNPjWKtsutF+BD8dXFVNug1rLsqlLKl86RGQRABDx8OXBn zIBQ== X-Gm-Message-State: AOAM531ePB/Ta2r1CENZnyDDEPSFLtFCLtHk6FZ5eKeQlj540A3EpVL1 2/lmEWRWhgtgmnLh/PhnmuyihHw= X-Google-Smtp-Source: ABdhPJwv1NZsciQAEcSrtC74h3wJYUa9g6KgVGsTRySeFuLsa5B3n+s9kih3ly3bm8jrsbGGSkrMFpU= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:538:aa52:9b59:413b]) (user=pcc job=sendgmr) by 2002:a05:6214:401e:: with SMTP id kd30mr24686995qvb.43.1627419282678; Tue, 27 Jul 2021 13:54:42 -0700 (PDT) Date: Tue, 27 Jul 2021 13:54:39 -0700 Message-Id: <20210727205439.2557419-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.32.0.432.gabb21c7263-goog Subject: [PATCH v5] arm64: avoid double ISB on kernel entry From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , Szabolcs Nagy , Tejas Belagod , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210727_135444_285344_6C4CBEC2 X-CRM114-Status: GOOD ( 12.33 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Although an ISB is required in order to make the MTE-related system register update to GCR_EL1 effective, and the same is true for PAC-related updates to SCTLR_EL1 or APIAKey{Hi,Lo}_EL1, we issue two ISBs on machines that support both features while we only need to issue one. To avoid the unnecessary additional ISB, remove the ISBs from the PAC and MTE-specific alternative blocks and add a couple of additional blocks that cause us to only execute one ISB if both features are supported. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/Idee7e8114d5ae5a0b171d06220a0eb4bb015a51c --- v5: - rebase onto 5.14rc3 v2: - fix formatting arch/arm64/kernel/entry.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index eacb9c01add0..102185eeeae0 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -176,7 +176,6 @@ alternative_else_nop_endif ldr_l \tmp, gcr_kernel_excl mte_set_gcr \tmp, \tmp2 - isb 1: #endif .endm @@ -250,12 +249,24 @@ alternative_if ARM64_HAS_ADDRESS_AUTH orr x0, x0, SCTLR_ELx_ENIA msr sctlr_el1, x0 2: - isb alternative_else_nop_endif #endif mte_set_kernel_gcr x22, x23 + /* + * Any non-self-synchronizing system register updates required for + * kernel entry should be placed before this point. + */ +alternative_if ARM64_MTE + isb + b 1f +alternative_else_nop_endif +alternative_if ARM64_HAS_ADDRESS_AUTH + isb +alternative_else_nop_endif +1: + scs_load tsk .else add x21, sp, #PT_REGS_SIZE