Message ID | 20210729082658.2815884-1-linus.walleij@linaro.org (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | ARM: dts: ixp4xx: Add devicetree for Linksys WRV54G | expand |
> + /* This set-up comes from an OpenWrt patch */ > + spi { > + compatible = "spi-gpio"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; > + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; > + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; > + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; > + num-chipselects = <1>; > + > + switch@0 { > + compatible = "micrel,ks8995"; Hi Linus This does not exist in mainline. And when it does, i guess it will be called microchip,ksz8995. See microchip,ksz.yaml. It is also missing all the ethernet-ports nodes. Maybe leave this out until the driver gets ported? > + /* > + * EthB - connected to the KS8995 switch ports 1-4 > + * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to > + * all four switch ports, also using an out of tree multiphy patch. > + * Do we need a new binding and property for this? > + */ This sounds like an issue with the KS8995 driver in OpenWRT. > + ethernet@c8009000 { > + status = "ok"; > + queue-rx = <&qmgr 3>; > + queue-txready = <&qmgr 20>; > + phy-mode = "rgmii"; > + phy-handle = <&phy4>; It looks like phy4 is a switch PHY. It is not actually connected to this MAC? So this is wrong for mainline. > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* Should be ports 1-4 on the KS8995 switch */ > + phy4: ethernet-phy@4 { > + reg = <4>; > + }; > + > + /* Should be port 5 on the KS8995 switch */ > + phy5: ethernet-phy@5 { > + reg = <5>; > + }; > + }; > + }; > + > + /* EthC - connected to KS8995 switch port 5 */ > + ethernet@c800a000 { > + status = "ok"; > + queue-rx = <&qmgr 4>; > + queue-txready = <&qmgr 21>; > + phy-mode = "rgmii"; > + phy-handle = <&phy5>; And i doubt this is correct. Unless there are back to back PHYs? I would suggest you leave out all the switch related properties until the switch driver is available. Andrew
On Thu, Jul 29, 2021 at 5:33 PM Andrew Lunn <andrew@lunn.ch> wrote: > > + /* This set-up comes from an OpenWrt patch */ > > + spi { > > + compatible = "spi-gpio"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; > > + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; > > + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; > > + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; > > + num-chipselects = <1>; > > + > > + switch@0 { > > + compatible = "micrel,ks8995"; > > Hi Linus > > This does not exist in mainline. And when it does, i guess it will be > called microchip,ksz8995. See microchip,ksz.yaml. As it happens it does exist, so this was what I was using: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/micrel-ks8995.txt > It is also missing > all the ethernet-ports nodes. Maybe leave this out until the driver > gets ported? The driver exists too: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/spi_ks8995.c Added in 2011: commit a8e510f682fe6d7671c11887e07c55f86caaf3c1 Author: Frederic LAMBERT <frdrc66@gmail.com> Date: Sun Dec 18 07:33:41 2011 +0000 phy: Micrel KS8995MA 5-ports 10/100 managed Ethernet switch support added Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Frederic Lambert <frdrc66@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> Notice: managed switch :/ that sounds like DSA. This was in 2011 so there was only the fringe Marvell DSA driver from Ben Hutchings. Then you & others started to work on DSA proper in 2014 IIUC. Then in 2016: commit 7e406d124c7935ee0238b957ea7e563dc1710f29 Author: Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Date: Tue Feb 9 20:47:18 2016 +0100 dt-bindings: net: ks8995: add bindings documentation for ks8995 Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> The bindings sneaked in. > > + /* > > + * EthB - connected to the KS8995 switch ports 1-4 > > + * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to > > + * all four switch ports, also using an out of tree multiphy patch. > > + * Do we need a new binding and property for this? > > + */ > > This sounds like an issue with the KS8995 driver in OpenWRT. The way I understand it is that the IXP4xx provides 4 "logical" ports and then one MII out to the ks8995 phy. I guess something predating the renewed DSA work. > > + ethernet@c8009000 { > > + status = "ok"; > > + queue-rx = <&qmgr 3>; > > + queue-txready = <&qmgr 20>; > > + phy-mode = "rgmii"; > > + phy-handle = <&phy4>; > > It looks like phy4 is a switch PHY. It is not actually connected to > this MAC? So this is wrong for mainline. I guess yes, but mainline seemingly has a switch-phy driver for it. > > + /* Should be port 5 on the KS8995 switch */ > > + phy5: ethernet-phy@5 { > > + reg = <5>; > > + }; > > + }; > > + }; > > + > > + /* EthC - connected to KS8995 switch port 5 */ > > + ethernet@c800a000 { > > + status = "ok"; > > + queue-rx = <&qmgr 4>; > > + queue-txready = <&qmgr 21>; > > + phy-mode = "rgmii"; > > + phy-handle = <&phy5>; > > And i doubt this is correct. Unless there are back to back PHYs? I think the WAN port is connected through its own MII to the KS8955 phy, it's my impression after looking at some of the product info and code. So the WAN port will actually work fine, but I don't know about the other 4 ports. > I would suggest you leave out all the switch related properties until > the switch driver is available. Sadly it is available. What shall we do with drivers/net/phy/spi_ks8995.c? Shall we just delete it (and the bindings) and tell people to go and write a DSA switch instead? (I don't know how Frederic and Helmuth would feel about that, so we need to discuss it.) Yours, Linus Walleij
Just a separate mail to clarify the genealogy here: On Thu, Jul 29, 2021 at 5:33 PM Andrew Lunn <andrew@lunn.ch> wrote: > > + switch@0 { > > + compatible = "micrel,ks8995"; (...) i guess it will be > called microchip,ksz8995. See microchip,ksz.yaml. Is it established that Microchip acquired Micrel and renamed the ks8995 product into ksz8995 so we are talking about the same physical, compatible component here? Yours, Linus Walleij
On Fri, Jul 30, 2021 at 02:15:57PM +0200, Linus Walleij wrote: > On Thu, Jul 29, 2021 at 5:33 PM Andrew Lunn <andrew@lunn.ch> wrote: > > > > + /* This set-up comes from an OpenWrt patch */ > > > + spi { > > > + compatible = "spi-gpio"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; > > > + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; > > > + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; > > > + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; > > > + num-chipselects = <1>; > > > + > > > + switch@0 { > > > + compatible = "micrel,ks8995"; > > > > Hi Linus > > > > This does not exist in mainline. And when it does, i guess it will be > > called microchip,ksz8995. See microchip,ksz.yaml. > > As it happens it does exist, so this was what I was using: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/micrel-ks8995.txt Ah, that driver! O.K. I will take a second look at this. I suspect there is code in userspace actually driving the switch. Andrew
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ac8a4a77584d..c01a8f55892f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -241,6 +241,7 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorcp.dtb dtb-$(CONFIG_ARCH_IXP4XX) += \ intel-ixp42x-linksys-nslu2.dtb \ + intel-ixp42x-linksys-wrv54g.dtb \ intel-ixp42x-welltech-epbx100.dtb \ intel-ixp42x-ixdp425.dtb \ intel-ixp43x-kixrp435.dtb \ diff --git a/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts new file mode 100644 index 000000000000..6b28dda747fd --- /dev/null +++ b/arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: ISC +/* + * Device Tree file for the Linksys WRV54G router + * Also known as Gemtek GTWX5715 + * Based on a board file by George T. Joseph and other patches. + * This machine is based on IXP425. + */ + +/dts-v1/; + +#include "intel-ixp42x.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Linksys WRV54G / Gemtek GTWX5715"; + compatible = "linksys,wrv54g", "gemtek,gtwx5715", "intel,ixp42x"; + #address-cells = <1>; + #size-cells = <1>; + + memory@0 { + /* 32 MB memory */ + device_type = "memory"; + reg = <0x00000000 0x2000000>; + }; + + chosen { + bootargs = "console=ttyS0,115200n8"; + stdout-path = "uart1:115200n8"; + }; + + aliases { + /* UART2 is the primary console */ + serial0 = &uart1; + serial1 = &uart0; + }; + + /* There is an unpopulated LED slot (3) connected to GPIO 8 */ + leds { + compatible = "gpio-leds"; + led-power { + label = "wrv54g:yellow:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + led-wireless { + label = "wrv54g:yellow:wireless"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led-internet { + label = "wrv54g:yellow:internet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + led-dmz { + label = "wrv54g:green:dmz"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; + + /* This set-up comes from an OpenWrt patch */ + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + + sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + num-chipselects = <1>; + + switch@0 { + compatible = "micrel,ks8995"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + soc { + bus@c4000000 { + flash@0,0 { + compatible = "intel,ixp4xx-flash", "cfi-flash"; + bank-width = <2>; + /* Enable writes on the expansion bus */ + intel,ixp4xx-eb-write-enable = <1>; + /* 8 MB of Flash mapped in at CS0 */ + reg = <0 0x00000000 0x00800000>; + + partitions { + compatible = "fixed-partitions"; + /* + * Partition info from a boot log + * CHECKME: not using redboot? FIS index 0x3f @7e00000? + */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "boot"; + reg = <0x0 0x140000>; + read-only; + }; + partition@140000 { + label = "linux"; + reg = <0x140000 0x100000>; + read-only; + }; + partition@240000 { + label = "root"; + reg = <0x240000 0x480000>; + read-write; + }; + }; + }; + }; + + pci@c0000000 { + status = "ok"; + + /* + * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. + * Derived from the GTWX5715 PCI boardfile. + */ + interrupt-map = + /* IDSEL 0 */ + <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */ + <0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */ + /* IDSEL 1 */ + <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ + <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */ + }; + + /* + * EthB - connected to the KS8995 switch ports 1-4 + * FIXME: the boardfile defines .phy_mask = 0x1e for this port to enable output to + * all four switch ports, also using an out of tree multiphy patch. + * Do we need a new binding and property for this? + */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy4>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Should be ports 1-4 on the KS8995 switch */ + phy4: ethernet-phy@4 { + reg = <4>; + }; + + /* Should be port 5 on the KS8995 switch */ + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; + + /* EthC - connected to KS8995 switch port 5 */ + ethernet@c800a000 { + status = "ok"; + queue-rx = <&qmgr 4>; + queue-txready = <&qmgr 21>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + }; + }; +};
This adds a device tree for the Linksys WRV54G also known as Gemtek GTWX5715. Some enhancements have been folded in from the OpenWrt patches. This supports everything in the upstream kernel with placeholders for the out-of-tree multiphy which exist in OpenWrt. Cc: phj@phj.hu Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/intel-ixp42x-linksys-wrv54g.dts | 173 ++++++++++++++++++ 2 files changed, 174 insertions(+) create mode 100644 arch/arm/boot/dts/intel-ixp42x-linksys-wrv54g.dts