@@ -512,6 +512,83 @@ pru1_1: pru@38000 {
firmware-name = "am437x-pru1_1-fw";
};
};
+
+ pruss0: pruss@40000 {
+ compatible = "ti,am4376-pruss0";
+ reg = <0x40000 0x40000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pruss0_mem: memories@40000 {
+ reg = <0x40000 0x1000>,
+ <0x42000 0x1000>;
+ reg-names = "dram0", "dram1";
+ };
+
+ pruss0_cfg: cfg@66000 {
+ compatible = "ti,pruss-cfg", "syscon";
+ reg = <0x66000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x66000 0x2000>;
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pruss0_iepclk_mux: iepclk-mux@30 {
+ reg = <0x30>;
+ #clock-cells = <0>;
+ clocks = <&sysclk_div>, /* icss_iep_gclk */
+ <&pruss_ocp_gclk>; /* icss_ocp_gclk */
+ };
+ };
+ };
+
+ pruss0_mii_rt: mii-rt@72000 {
+ compatible = "ti,pruss-mii", "syscon";
+ reg = <0x72000 0x58>;
+ status = "disabled";
+ };
+
+ pruss0_intc: interrupt-controller@60000 {
+ compatible = "ti,pruss-intc";
+ reg = <0x60000 0x2000>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host_intr0", "host_intr1",
+ "host_intr2", "host_intr3",
+ "host_intr4",
+ "host_intr6", "host_intr7";
+ ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
+ };
+
+ pru0_0: pru@74000 {
+ compatible = "ti,am4376-pru";
+ reg = <0x74000 0x1000>,
+ <0x62000 0x400>,
+ <0x62400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am437x-pru0_0-fw";
+ };
+
+ pru0_1: pru@78000 {
+ compatible = "ti,am4376-pru";
+ reg = <0x78000 0x1000>,
+ <0x64000 0x400>,
+ <0x64400 0x100>;
+ reg-names = "iram", "control", "debug";
+ firmware-name = "am437x-pru0_1-fw";
+ };
+ };
};
target-module@50000000 {
The AM4376+ SoCs have a second smaller PRU-ICSS subsystem (PRUSS0) in addition to the primary PRUSS1 instance. The PRUSS0 has less DRAM per PRU, and no Shared DRAM among other minor differences. The IEP and MII_RT modules even though present within the IP are not pinned out. This PRUSS0 instance has a weird SoC integration. It shares the same L3 OCP interconnect interface with PRUSS1, and also shares its reset line and clocks. Any external accesses from PRUSS0 requires the PRUSS1's PRUSS_SYSCFG register to be programmed properly. That said, it is its own IP instance (a cut-down version), and so it has been added as an independent node (sibling node to PRUSS1 node) and a child node of the corresponding PRUSS target module interconnect node. This allows the PRUSS0 instance to be enabled/disabled independently of the PRUSS1 instance. The nodes are added under the corresponding interconnect target module node in the common am4372 dtsi file. The PRU-ICSS instances are not supported on AM4372 SoC though in the AM437x family, so the interconnect target module node should be disabled in any derivative board dts file that uses AM4372 SoCs. The individual PRUSS node can be disabled in the corresponding board dts file if desired. The default names for the firmware images for each PRU core are defined as follows (these can be adjusted either in derivative board dts files or through sysfs at runtime if required): PRU-ICSS0 PRU0 Core: am437x-pru0_0-fw PRU-ICSS0 PRU1 Core: am437x-pru0_1-fw Note: 1. There are few more sub-modules like the Industrial Ethernet Peripheral (IEP), eCAP, UART, that do not have bindings and so will be added in the future. Only UART is pinned out, so others should be added in disabled state if added. 2. The PRUSS0 INTC on AM437x SoCs routes the host interrupt 5 to the other PRUSS1, so it is already marked reserved through the 'ti,irqs-reserved' property. Signed-off-by: Suman Anna <s-anna@ti.com> --- arch/arm/boot/dts/am4372.dtsi | 77 +++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+)