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Sat, 31 Jul 2021 02:24:35 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyaUYFBiBXOj/YrSnv2G1IxSRpz8mT9DY7R7LnPnM3pnBBdSPX26G/dea1pdGER5HCdqQwzig== X-Received: by 2002:a05:6402:28f:: with SMTP id l15mr8056962edv.131.1627723475618; Sat, 31 Jul 2021 02:24:35 -0700 (PDT) Received: from localhost.localdomain ([86.32.47.9]) by smtp.gmail.com with ESMTPSA id r16sm1947693edt.15.2021.07.31.02.24.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Jul 2021 02:24:35 -0700 (PDT) From: Krzysztof Kozlowski To: Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Marek Szyprowski , Sylwester Nawrocki , Bartlomiej Zolnierkiewicz , Chanwoo Choi , Alim Akhtar Subject: [PATCH 2/8] ARM: dts: exynos: add CPU topology to Exynos4210 Date: Sat, 31 Jul 2021 11:24:03 +0200 Message-Id: <20210731092409.31496-2-krzysztof.kozlowski@canonical.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20210731092409.31496-1-krzysztof.kozlowski@canonical.com> References: <20210731092409.31496-1-krzysztof.kozlowski@canonical.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210731_022441_298848_99EBA892 X-CRM114-Status: GOOD ( 12.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Describe Exynos4210 CPU topology. Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 70baad9b11f0..7e7d65ce6585 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -32,6 +32,17 @@ cpus { #address-cells = <1>; #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + cpu0: cpu@900 { device_type = "cpu"; compatible = "arm,cortex-a9";