diff mbox series

[V7,4/7] ARM: dts: imx6q-dhcom: Cleanup of the devicetrees

Message ID 20210802141038.59663-4-cniedermaier@dh-electronics.com (mailing list archive)
State New, archived
Headers show
Series [V7,1/7] ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board | expand

Commit Message

Christoph Niedermaier Aug. 2, 2021, 2:10 p.m. UTC 
Following cleanups of the devicetrees done, no change in function:
- Remove parentheses from the license
- Update copyright date
- Alphabetical sorting
- Add comments
- Update pinctrl names
- Hex values in lower case
- Set 3rd values of fixed regulators gpio property to 0
- Replace interrupt type with a define
- Remove superfluous property max-speed from the fec node

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: kernel@dh-electronics.com
To: linux-arm-kernel@lists.infradead.org
---
V2: - Set 3rd values of fixed regulators gpio property to 0
    - Rebase on Shawn Guos branch for-next
V3: - Remove superfluous property max-speed from the fec node
    - Add Reviewed-by tag
V4: - No changes
V5: - No changes
V6: - Rebase on 5.14-rc1
V7: - Rebase on Shawn Guos branch for-next
---
 arch/arm/boot/dts/imx6q-dhcom-pdk2.dts |  90 +++++-----
 arch/arm/boot/dts/imx6q-dhcom-som.dtsi | 302 +++++++++++++++++----------------
 2 files changed, 204 insertions(+), 188 deletions(-)

Comments

Shawn Guo Aug. 9, 2021, 7:35 a.m. UTC | #1 
On Mon, Aug 02, 2021 at 04:10:35PM +0200, Christoph Niedermaier wrote:
> Following cleanups of the devicetrees done, no change in function:
> - Remove parentheses from the license
> - Update copyright date
> - Alphabetical sorting
> - Add comments
> - Update pinctrl names
> - Hex values in lower case
> - Set 3rd values of fixed regulators gpio property to 0
> - Replace interrupt type with a define
> - Remove superfluous property max-speed from the fec node
> 
> Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
> Reviewed-by: Marek Vasut <marex@denx.de>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <festevam@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: NXP Linux Team <linux-imx@nxp.com>
> Cc: kernel@dh-electronics.com
> To: linux-arm-kernel@lists.infradead.org

Applied, thanks!
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
index 897bbeb91d64..4b8801e91bd4 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
+++ b/arch/arm/boot/dts/imx6q-dhcom-pdk2.dts
@@ -1,6 +1,6 @@ 
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  */
 
@@ -18,27 +18,27 @@ 
 	};
 
 	clk_ext_audio_codec: clock-codec {
-		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		clock-frequency = <24000000>;
+		compatible = "fixed-clock";
 	};
 
 	display_bl: display-bl {
-		compatible = "pwm-backlight";
-		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
 		brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
+		compatible = "pwm-backlight";
 		default-brightness-level = <8>;
-		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+		enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>; /* GPIO G */
+		pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
 		status = "okay";
 	};
 
 	lcd_display: disp0 {
-		compatible = "fsl,imx-parallel-display";
 		#address-cells = <1>;
 		#size-cells = <0>;
+		compatible = "fsl,imx-parallel-display";
 		interface-pix-fmt = "rgb24";
-		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_ipu1_lcdif &pinctrl_dhcom_g>;
+		pinctrl-names = "default";
 		status = "okay";
 
 		port@0 {
@@ -63,36 +63,36 @@ 
 		compatible = "gpio-keys";
 
 		button-0 {
+			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* GPIO A */
 			label = "TA1-GPIO-A";
 			linux,code = <KEY_A>;
-			gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_a>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-1 {
+			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; /* GPIO B */
 			label = "TA2-GPIO-B";
 			linux,code = <KEY_B>;
-			gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_b>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-2 {
+			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; /* GPIO C */
 			label = "TA3-GPIO-C";
 			linux,code = <KEY_C>;
-			gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_c>;
 			pinctrl-names = "default";
 			wakeup-source;
 		};
 
 		button-3 {
+			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; /* GPIO D */
 			label = "TA4-GPIO-D";
 			linux,code = <KEY_D>;
-			gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
 			pinctrl-0 = <&pinctrl_dhcom_d>;
 			pinctrl-names = "default";
 			wakeup-source;
@@ -108,9 +108,9 @@ 
 		 */
 		led-5 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; /* GPIO E */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_e>;
 			pinctrl-names = "default";
 			status = "disabled";
@@ -118,35 +118,35 @@ 
 
 		led-6 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO F */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_f>;
 			pinctrl-names = "default";
 		};
 
 		led-7 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* GPIO H */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_h>;
 			pinctrl-names = "default";
 		};
 
 		led-8 {
 			color = <LED_COLOR_ID_GREEN>;
+			default-state = "off";
 			function = LED_FUNCTION_INDICATOR;
 			gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */
-			default-state = "off";
 			pinctrl-0 = <&pinctrl_dhcom_i>;
 			pinctrl-names = "default";
 		};
 	};
 
 	panel {
-		compatible = "edt,etm0700g0edh6";
 		backlight = <&display_bl>;
+		compatible = "edt,etm0700g0edh6";
 
 		port {
 			lcd_panel_in: endpoint {
@@ -156,23 +156,23 @@ 
 	};
 
 	sound {
-		compatible = "fsl,imx-audio-sgtl5000";
-		model = "imx-sgtl5000";
-		ssi-controller = <&ssi1>;
 		audio-codec = <&sgtl5000>;
 		audio-routing =
 			"MIC_IN", "Mic Jack",
 			"Mic Jack", "Mic Bias",
 			"LINE_IN", "Line In Jack",
 			"Headphone Jack", "HP_OUT";
-		mux-int-port = <1>;
+		compatible = "fsl,imx-audio-sgtl5000";
+		model = "imx-sgtl5000";
 		mux-ext-port = <3>;
+		mux-int-port = <1>;
+		ssi-controller = <&ssi1>;
 	};
 };
 
 &audmux {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_audmux_ext>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -189,8 +189,8 @@ 
 &fec {
 	phy-mode = "rgmii";
 	phy-handle = <&ethphy7>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_1G>;
+	pinctrl-names = "default";
 	status = "okay";
 
 	mdio {
@@ -204,20 +204,20 @@ 
 			pinctrl-0 = <&pinctrl_ethphy7>;
 			pinctrl-names = "default";
 			reg = <7>;
-			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 			rxc-skew-ps = <3000>;
 			rxd0-skew-ps = <0>;
 			rxd1-skew-ps = <0>;
 			rxd2-skew-ps = <0>;
 			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
 			txc-skew-ps = <3000>;
 			txd0-skew-ps = <0>;
 			txd1-skew-ps = <0>;
 			txd2-skew-ps = <0>;
 			txd3-skew-ps = <0>;
-			rxdv-skew-ps = <0>;
 			txen-skew-ps = <0>;
 		};
 	};
@@ -230,21 +230,21 @@ 
 
 &i2c2 {
 	sgtl5000: codec@a {
-		compatible = "fsl,sgtl5000";
-		reg = <0x0a>;
 		#sound-dai-cells = <0>;
 		clocks = <&clk_ext_audio_codec>;
+		compatible = "fsl,sgtl5000";
+		reg = <0x0a>;
 		VDDA-supply = <&reg_3p3v>;
 		VDDIO-supply = <&sw2_reg>;
 	};
 
 	touchscreen@38 {
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_dhcom_e>;
 		compatible = "edt,edt-ft5406";
-		reg = <0x38>;
 		interrupt-parent = <&gpio4>;
 		interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
+		pinctrl-0 = <&pinctrl_dhcom_e>;
+		pinctrl-names = "default";
+		reg = <0x38>;
 	};
 };
 
@@ -254,13 +254,13 @@ 
 
 &pcie {
 	pinctrl-0 = <&pinctrl_pcie &pinctrl_dhcom_j>;
-	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
+	reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>; /* GPIO J */
 	status = "okay";
 };
 
 &pwm1 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -272,12 +272,11 @@ 
 	status = "okay";
 };
 
-&usdhc3 {
+&usdhc3 { /* Micro SD card on module */
 	status = "okay";
 };
 
 &iomuxc {
-	pinctrl-names = "default";
 	pinctrl-0 = <
 			/*
 			 * The following DHCOM GPIOs are used on this board.
@@ -300,50 +299,51 @@ 
 			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
 			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
+	pinctrl-names = "default";
 
 	pinctrl_audmux_ext: audmux-ext-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
 			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
 			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
 			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
+			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
 		>;
 	};
 
 	pinctrl_enet_1G: enet-1G-grp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
 			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
 			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
 			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
 			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
 		>;
 	};
 
 	pinctrl_ethphy7: ethphy7-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0xb0 /* Reset */
 			MX6QDL_PAD_GPIO_0__GPIO1_IO00		0xb1 /* Int */
-			MX6QDL_PAD_EIM_D26__GPIO3_IO26		0xb1 /* WOL */
 		>;
 	};
 
 	pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
 		fsl,pins = <
 			MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK	0x38
-			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
 			MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02		0x38
 			MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03		0x38
+			MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15		0x38
 			MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00	0x38
 			MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01	0x38
 			MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02	0x38
diff --git a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
index 829f31bc569d..99a275e06643 100644
--- a/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
+++ b/arch/arm/boot/dts/imx6q-dhcom-som.dtsi
@@ -1,6 +1,6 @@ 
-// SPDX-License-Identifier: (GPL-2.0+)
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2015 DH electronics GmbH
+ * Copyright (C) 2015-2021 DH electronics GmbH
  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
  */
 
@@ -28,14 +28,22 @@ 
 		serial4 = &uart3;
 	};
 
-	memory@10000000 {
+	memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
 		device_type = "memory";
 		reg = <0x10000000 0x20000000>;
 	};
 
+	reg_3p3v: regulator-3P3V {
+		compatible = "regulator-fixed";
+		regulator-always-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-name = "3P3V";
+	};
+
 	reg_eth_vio: regulator-eth-vio {
 		compatible = "regulator-fixed";
-		gpio = <&gpio1 7 GPIO_ACTIVE_LOW>;
+		gpio = <&gpio1 7 0>;
 		pinctrl-0 = <&pinctrl_enet_vio>;
 		pinctrl-names = "default";
 		regulator-always-on;
@@ -54,86 +62,84 @@ 
 		regulator-name = "latch_oe_on";
 	};
 
-	reg_usb_otg_vbus: regulator-usb-otg-vbus {
+	reg_usb_h1_vbus: regulator-usb-h1-vbus {
 		compatible = "regulator-fixed";
-		regulator-name = "usb_otg_vbus";
+		enable-active-high;
+		gpio = <&gpio3 31 0>;
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
+		regulator-name = "usb_h1_vbus";
 	};
 
-	reg_usb_h1_vbus: regulator-usb-h1-vbus {
+	reg_usb_otg_vbus: regulator-usb-otg-vbus {
 		compatible = "regulator-fixed";
-		regulator-name = "usb_h1_vbus";
 		regulator-min-microvolt = <5000000>;
 		regulator-max-microvolt = <5000000>;
-		gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	reg_3p3v: regulator-3P3V {
-		compatible = "regulator-fixed";
-		regulator-name = "3P3V";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
+		regulator-name = "usb_otg_vbus";
 	};
 };
 
 &can1 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan1>;
+	pinctrl-names = "default";
 };
 
+/*
+ * Special hardware required which uses the pins from micro SD card. The pins
+ * SD3_DAT0 and SD3_DAT1 are muxed as can2 Tx and Rx. The signals for can2 Tx
+ * and Rx are output on DHCOM uart1 rts/cts pins. So to enable can2 on the board
+ * device tree file, you also need to disable the micro SD card and the uart1
+ * rts/cts have to be disabled or output on other DHCOM pins.
+ */
 &can2 {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_flexcan2>;
+	pinctrl-names = "default";
 };
 
 &ecspi1 {
 	cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>, <&gpio4 11 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi1>;
+	pinctrl-names = "default";
 	status = "okay";
 
-	flash@0 {	/* S25FL116K */
+	flash@0 { /* S25FL116K */
 		#address-cells = <1>;
 		#size-cells = <1>;
 		compatible = "jedec,spi-nor";
-		spi-max-frequency = <50000000>;
-		reg = <0>;
 		m25p,fast-read;
+		reg = <0>;
+		spi-max-frequency = <50000000>;
 	};
 };
 
 &ecspi2 {
 	cs-gpios = <&gpio5 29 GPIO_ACTIVE_LOW>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_ecspi2>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
 &fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_enet_100M>;
 	phy-mode = "rmii";
 	phy-handle = <&ethphy0>;
+	pinctrl-0 = <&pinctrl_enet_100M>;
+	pinctrl-names = "default";
 	status = "okay";
 
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		ethphy0: ethernet-phy@0 {	/* SMSC LAN8710Ai */
+		ethphy0: ethernet-phy@0 { /* SMSC LAN8710Ai */
 			compatible = "ethernet-phy-ieee802.3-c22";
 			interrupt-parent = <&gpio4>;
 			interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
-			max-speed = <100>;
 			pinctrl-0 = <&pinctrl_ethphy0>;
 			pinctrl-names = "default";
 			reg = <0>;
-			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			reset-assert-us = <1000>;
 			reset-deassert-us = <1000>;
+			reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 			smsc,disable-energy-detect; /* Make plugin detection reliable */
 		};
 	};
@@ -196,139 +202,147 @@ 
 };
 
 &i2c1 {
+	/*
+	 * Info: According to erratum ERR007805 clock frequency limit is 375000.
+	 * The erratum for i.MX6S/DL is here [1] and for i.MX6Q/D is here [2].
+	 * [1] https://www.nxp.com/docs/en/errata/IMX6SDLCE.pdf
+	 * [2] https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
+	 */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
 	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
 &i2c2 {
+	/* Info: Clock frequency limit is 375000 (for details see i2c1) */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c2>;
 	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 };
 
 &i2c3 {
+	/* Info: Clock frequency limit is 375000 (for details see i2c1) */
 	clock-frequency = <100000>;
-	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c3>;
 	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	pinctrl-names = "default", "gpio";
 	scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 	status = "okay";
 
 	ltc3676: pmic@3c {
 		compatible = "lltc,ltc3676";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic_hw300>;
-		reg = <0x3c>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_pmic>;
+		pinctrl-names = "default";
+		reg = <0x3c>;
 
 		regulators {
 			sw1_reg: sw1 {
-				regulator-min-microvolt = <787500>;
-				regulator-max-microvolt = <1527272>;
 				lltc,fb-voltage-divider = <100000 110000>;
-				regulator-suspend-mem-microvolt = <1040000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1527272>;
+				regulator-min-microvolt = <787500>;
+				regulator-ramp-delay = <7000>;
+				regulator-suspend-mem-microvolt = <1040000>;
 			};
 
 			sw2_reg: sw2 {
-				regulator-min-microvolt = <1885714>;
-				regulator-max-microvolt = <3657142>;
 				lltc,fb-voltage-divider = <100000 28000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3657142>;
+				regulator-min-microvolt = <1885714>;
+				regulator-ramp-delay = <7000>;
 			};
 
 			sw3_reg: sw3 {
-				regulator-min-microvolt = <787500>;
-				regulator-max-microvolt = <1527272>;
 				lltc,fb-voltage-divider = <100000 110000>;
-				regulator-suspend-mem-microvolt = <980000>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1527272>;
+				regulator-min-microvolt = <787500>;
+				regulator-ramp-delay = <7000>;
+				regulator-suspend-mem-microvolt = <980000>;
 			};
 
 			sw4_reg: sw4 {
-				regulator-min-microvolt = <855571>;
-				regulator-max-microvolt = <1659291>;
 				lltc,fb-voltage-divider = <100000 93100>;
-				regulator-ramp-delay = <7000>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <1659291>;
+				regulator-min-microvolt = <855571>;
+				regulator-ramp-delay = <7000>;
 			};
 
 			ldo1_reg: ldo1 {
-				regulator-min-microvolt = <3240306>;
-				regulator-max-microvolt = <3240306>;
 				lltc,fb-voltage-divider = <102000 29400>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <3240306>;
+				regulator-min-microvolt = <3240306>;
 			};
 
 			ldo2_reg: ldo2 {
-				regulator-min-microvolt = <2484708>;
-				regulator-max-microvolt = <2484708>;
 				lltc,fb-voltage-divider = <100000 41200>;
-				regulator-boot-on;
 				regulator-always-on;
+				regulator-boot-on;
+				regulator-max-microvolt = <2484708>;
+				regulator-min-microvolt = <2484708>;
 			};
 		};
 	};
 
-	touchscreen@49 {	/* TSC2004 */
+	touchscreen@49 { /* TSC2004 */
 		compatible = "ti,tsc2004";
+		interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_tsc2004>;
+		pinctrl-names = "default";
 		reg = <0x49>;
 		vio-supply = <&reg_3p3v>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_tsc2004_hw300>;
-		interrupts-extended = <&gpio4 14 IRQ_TYPE_EDGE_FALLING>;
 		status = "disabled";
 	};
 
 	eeprom@50 {
 		compatible = "atmel,24c02";
-		reg = <0x50>;
 		pagesize = <16>;
+		reg = <0x50>;
 	};
 
 	rtc_i2c: rtc@56 {
 		compatible = "microcrystal,rv3029";
+		interrupt-parent = <&gpio7>;
+		interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+		pinctrl-0 = <&pinctrl_rtc>;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_rtc_hw300>;
 		reg = <0x56>;
-		interrupt-parent = <&gpio7>;
-		interrupts = <12 2>;
 	};
 };
 
 &pcie {
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pcie>;
+	pinctrl-names = "default";
 };
 
 &reg_arm {
 	vin-supply = <&sw3_reg>;
 };
 
-&reg_soc {
+&reg_pu {
 	vin-supply = <&sw1_reg>;
 };
 
-&reg_pu {
+&reg_soc {
 	vin-supply = <&sw1_reg>;
 };
 
@@ -340,71 +354,71 @@ 
 	vin-supply = <&sw2_reg>;
 };
 
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	uart-has-rtscts;
-	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
-	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+&uart1 { /* DHCOM UART1 */
 	dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+	dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+	dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
 	rng-gpios = <&gpio2 31 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pinctrl_uart1>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
 	status = "okay";
 };
 
-&uart4 {
-	pinctrl-names = "default";
+&uart4 { /* DHCOM UART3 */
 	pinctrl-0 = <&pinctrl_uart4>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
-&uart5 {
-	pinctrl-names = "default";
+&uart5 { /* DHCOM UART2 */
 	pinctrl-0 = <&pinctrl_uart5>;
+	pinctrl-names = "default";
 	uart-has-rtscts;
 	status = "okay";
 };
 
 &usbh1 {
-	pinctrl-names = "default";
+	dr_mode = "host";
 	pinctrl-0 = <&pinctrl_usbh1>;
+	pinctrl-names = "default";
 	vbus-supply = <&reg_usb_h1_vbus>;
-	dr_mode = "host";
 	status = "okay";
 };
 
 &usbotg {
-	vbus-supply = <&reg_usb_otg_vbus>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg>;
 	disable-over-current;
 	dr_mode = "otg";
+	pinctrl-0 = <&pinctrl_usbotg>;
+	pinctrl-names = "default";
+	vbus-supply = <&reg_usb_otg_vbus>;
 	status = "okay";
 };
 
-&usdhc2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc2>;
+&usdhc2 { /* External SD card via DHCOM */
 	cd-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
 	keep-power-in-suspend;
+	pinctrl-0 = <&pinctrl_usdhc2>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
-&usdhc3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc3>;
+&usdhc3 { /* Micro SD card on module */
 	cd-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>;
 	fsl,wp-controller;
 	keep-power-in-suspend;
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-names = "default";
 	status = "disabled";
 };
 
-&usdhc4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usdhc4>;
-	non-removable;
+&usdhc4 { /* eMMC on module */
 	bus-width = <8>;
-	no-1-8-v;
 	keep-power-in-suspend;
+	no-1-8-v;
+	non-removable;
+	pinctrl-0 = <&pinctrl_usdhc4>;
+	pinctrl-names = "default";
 	status = "okay";
 };
 
@@ -412,8 +426,8 @@ 
 	#address-cells = <2>;
 	#size-cells = <1>;
 	fsl,weim-cs-gpr = <&gpr>;
-	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_weim &pinctrl_weim_cs0 &pinctrl_weim_cs1>;
+	pinctrl-names = "default";
 	/* It is necessary to setup 2x 64MB otherwise setting gpr fails */
 	ranges = <0 0 0x08000000 0x04000000>, /* CS0 */
 		 <1 0 0x0c000000 0x04000000>; /* CS1 */
@@ -421,7 +435,6 @@ 
 };
 
 &iomuxc {
-	pinctrl-names = "default";
 	pinctrl-0 = <
 			&pinctrl_hog_base
 			&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
@@ -433,14 +446,17 @@ 
 			&pinctrl_dhcom_s &pinctrl_dhcom_t &pinctrl_dhcom_u
 			&pinctrl_dhcom_v &pinctrl_dhcom_w &pinctrl_dhcom_int
 		>;
+	pinctrl-names = "default";
 
 	pinctrl_hog_base: hog-base-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0x120b0
-			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x120b0
-			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x120b0
+			/* GPIOs for memory coding */
 			MX6QDL_PAD_EIM_A16__GPIO2_IO22		0x120b0
 			MX6QDL_PAD_EIM_A17__GPIO2_IO21		0x120b0
+			/* GPIOs for hardware coding */
+			MX6QDL_PAD_EIM_A19__GPIO2_IO19		0x120b0
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x120b0
+			MX6QDL_PAD_EIM_A23__GPIO6_IO06		0x120b0
 		>;
 	};
 
@@ -543,9 +559,9 @@ 
 
 	pinctrl_ecspi1: ecspi1-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
 			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
 			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
-			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x100b1
 			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
 			MX6QDL_PAD_KEY_ROW2__GPIO4_IO11		0x1b0b0
 		>;
@@ -553,18 +569,18 @@ 
 
 	pinctrl_ecspi2: ecspi2-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO	0x100b1
-			MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI	0x100b1
 			MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK	0x100b1
+			MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI	0x100b1
+			MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO	0x100b1
 			MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29	0x1b0b0
 		>;
 	};
 
 	pinctrl_enet_100M: enet-100M-grp {
 		fsl,pins = <
-			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
-			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
 			MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
 			MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
 			MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
@@ -590,8 +606,8 @@ 
 
 	pinctrl_flexcan1: flexcan1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
 			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX		0x1b0b0
+			MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX	0x1b0b0
 		>;
 	};
 
@@ -644,40 +660,40 @@ 
 		>;
 	};
 
-	pinctrl_pmic_hw300: pmic-hw300-grp {
+	pinctrl_pcie: pcie-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1B0B0
+			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
 		>;
 	};
 
-	pinctrl_rtc_hw300: rtc-hw300-grp {
+	pinctrl_pmic: pmic-grp {
 		fsl,pins = <
-			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120B0
+			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x1b0b0
 		>;
 	};
 
-	pinctrl_tsc2004_hw300: tsc2004-hw300-grp {
+	pinctrl_rtc: rtc-grp {
 		fsl,pins = <
-			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x120B0
+			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x120b0
 		>;
 	};
 
-	pinctrl_pcie: pcie-grp {
+	pinctrl_tsc2004: tsc2004-grp {
 		fsl,pins = <
-			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b1 /* Wake */
+			MX6QDL_PAD_KEY_COL4__GPIO4_IO14		0x120b0
 		>;
 	};
 
 	pinctrl_uart1: uart1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
-			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
-			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
 			MX6QDL_PAD_EIM_D19__UART1_CTS_B		0x4001b0b1
+			MX6QDL_PAD_EIM_D20__UART1_RTS_B		0x1b0b1
 			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x4001b0b1
 			MX6QDL_PAD_EIM_D24__GPIO3_IO24		0x4001b0b1
 			MX6QDL_PAD_EIM_D25__GPIO3_IO25		0x4001b0b1
 			MX6QDL_PAD_EIM_EB3__GPIO2_IO31		0x4001b0b1
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
 		>;
 	};
 
@@ -699,7 +715,7 @@ 
 
 	pinctrl_usbh1: usbh1-grp {
 		fsl,pins = <
-			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x120B0
+			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x120b0
 		>;
 	};
 
@@ -711,32 +727,32 @@ 
 
 	pinctrl_usdhc2: usdhc2-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
+			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x120b0
 			MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
+			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
 			MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
 			MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
 			MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
 			MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
-			MX6QDL_PAD_NANDF_CS3__GPIO6_IO16	0x120B0
 		>;
 	};
 
 	pinctrl_usdhc3: usdhc3-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
 			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
 			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
 			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
 			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
-			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x120B0
+			MX6QDL_PAD_SD3_RST__GPIO7_IO08		0x120b0
 		>;
 	};
 
 	pinctrl_usdhc4: usdhc4-grp {
 		fsl,pins = <
-			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
 			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
+			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
 			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
 			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
 			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
@@ -750,26 +766,26 @@ 
 
 	pinctrl_weim: weim-grp {
 		fsl,pins = <
+			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0a6
+			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0a6
+			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0a6
+			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0a6
+			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0a6
+			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0a6
+			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0a6
+			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0a6
+			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0a6
+			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0a6
+			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0a6
+			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0a6
+			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0a6
+			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0a6
+			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0a6
+			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0a6
+			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
+			MX6QDL_PAD_EIM_LBA__EIM_LBA_B		0xb060 /* LE */
 			MX6QDL_PAD_EIM_OE__EIM_OE_B		0xb0a6
 			MX6QDL_PAD_EIM_RW__EIM_RW		0xb0a6 /* WE */
-			MX6QDL_PAD_EIM_LBA__EIM_LBA_B		0xb060 /* LE */
-			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x130b0
-			MX6QDL_PAD_EIM_DA15__EIM_AD15		0xb0a6
-			MX6QDL_PAD_EIM_DA14__EIM_AD14		0xb0a6
-			MX6QDL_PAD_EIM_DA13__EIM_AD13		0xb0a6
-			MX6QDL_PAD_EIM_DA12__EIM_AD12		0xb0a6
-			MX6QDL_PAD_EIM_DA11__EIM_AD11		0xb0a6
-			MX6QDL_PAD_EIM_DA10__EIM_AD10		0xb0a6
-			MX6QDL_PAD_EIM_DA9__EIM_AD09		0xb0a6
-			MX6QDL_PAD_EIM_DA8__EIM_AD08		0xb0a6
-			MX6QDL_PAD_EIM_DA7__EIM_AD07		0xb0a6
-			MX6QDL_PAD_EIM_DA6__EIM_AD06		0xb0a6
-			MX6QDL_PAD_EIM_DA5__EIM_AD05		0xb0a6
-			MX6QDL_PAD_EIM_DA4__EIM_AD04		0xb0a6
-			MX6QDL_PAD_EIM_DA3__EIM_AD03		0xb0a6
-			MX6QDL_PAD_EIM_DA2__EIM_AD02		0xb0a6
-			MX6QDL_PAD_EIM_DA1__EIM_AD01		0xb0a6
-			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0a6
 		>;
 	};