Message ID | 20210804085819.846610-17-oupton@google.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | KVM: Add idempotent controls for migrating system counter state | expand |
On Wed, 04 Aug 2021 09:58:14 +0100, Oliver Upton <oupton@google.com> wrote: > > Introduce a new cpucap to indicate if the system supports full enhanced > counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2). > > Signed-off-by: Oliver Upton <oupton@google.com> > --- > arch/arm64/include/asm/sysreg.h | 2 ++ > arch/arm64/kernel/cpufeature.c | 10 ++++++++++ > arch/arm64/tools/cpucaps | 1 + > 3 files changed, 13 insertions(+) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 7b9c3acba684..4dfc44066dfb 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -847,6 +847,8 @@ > #define ID_AA64MMFR0_ASID_SHIFT 4 > #define ID_AA64MMFR0_PARANGE_SHIFT 0 > > +#define ID_AA64MMFR0_ECV_VIRT 0x1 > +#define ID_AA64MMFR0_ECV_PHYS 0x2 > #define ID_AA64MMFR0_TGRAN4_NI 0xf > #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 > #define ID_AA64MMFR0_TGRAN64_NI 0xf > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 0ead8bfedf20..94c349e179d3 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > + { > + .desc = "Enhanced Counter Virtualization (Physical)", > + .capability = ARM64_ECV, > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > + .sys_reg = SYS_ID_AA64MMFR0_EL1, > + .sign = FTR_UNSIGNED, > + .field_pos = ID_AA64MMFR0_ECV_SHIFT, > + .matches = has_cpuid_feature, > + .min_field_value = ID_AA64MMFR0_ECV_PHYS, > + }, > {}, > }; > > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 49305c2e6dfd..d819ea614da5 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -3,6 +3,7 @@ > # Internal CPU capabilities constants, keep this list sorted > > BTI > +ECV > # Unreliable: use system_supports_32bit_el0() instead. > HAS_32BIT_EL0_DO_NOT_USE > HAS_32BIT_EL1 As discussed in another context, we probably want both ECV and ECV2 to distinguish the two feature sets that ECV has so far. Thanks, M.
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7b9c3acba684..4dfc44066dfb 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -847,6 +847,8 @@ #define ID_AA64MMFR0_ASID_SHIFT 4 #define ID_AA64MMFR0_PARANGE_SHIFT 0 +#define ID_AA64MMFR0_ECV_VIRT 0x1 +#define ID_AA64MMFR0_ECV_PHYS 0x2 #define ID_AA64MMFR0_TGRAN4_NI 0xf #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 #define ID_AA64MMFR0_TGRAN64_NI 0xf diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 0ead8bfedf20..94c349e179d3 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2301,6 +2301,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .matches = has_cpuid_feature, .min_field_value = 1, }, + { + .desc = "Enhanced Counter Virtualization (Physical)", + .capability = ARM64_ECV, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .sys_reg = SYS_ID_AA64MMFR0_EL1, + .sign = FTR_UNSIGNED, + .field_pos = ID_AA64MMFR0_ECV_SHIFT, + .matches = has_cpuid_feature, + .min_field_value = ID_AA64MMFR0_ECV_PHYS, + }, {}, }; diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 49305c2e6dfd..d819ea614da5 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -3,6 +3,7 @@ # Internal CPU capabilities constants, keep this list sorted BTI +ECV # Unreliable: use system_supports_32bit_el0() instead. HAS_32BIT_EL0_DO_NOT_USE HAS_32BIT_EL1
Introduce a new cpucap to indicate if the system supports full enhanced counter virtualization (i.e. ID_AA64MMFR0_EL1.ECV==0x2). Signed-off-by: Oliver Upton <oupton@google.com> --- arch/arm64/include/asm/sysreg.h | 2 ++ arch/arm64/kernel/cpufeature.c | 10 ++++++++++ arch/arm64/tools/cpucaps | 1 + 3 files changed, 13 insertions(+)