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Thu, 5 Aug 2021 17:43:06 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Thu, 5 Aug 2021 10:42:55 -0700 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.2176.2 via Frontend Transport; Thu, 5 Aug 2021 10:42:55 -0700 Received: from [10.140.6.35] (port=51088 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1mBhOP-0005Bw-P9; Thu, 05 Aug 2021 10:42:54 -0700 From: Piyush Mehta To: , , , , , , , , , CC: , , , , , , Piyush Mehta Subject: [PATCH V2 2/3] dt-bindings: gpio: zynqmp: Add binding documentation for modepin Date: Thu, 5 Aug 2021 23:12:18 +0530 Message-ID: <20210805174219.3000667-3-piyush.mehta@xilinx.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210805174219.3000667-1-piyush.mehta@xilinx.com> References: <20210805174219.3000667-1-piyush.mehta@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8b3ee291-671e-4152-d1db-08d958387b78 X-MS-TrafficTypeDiagnostic: DM8PR02MB8155: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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Modepin GPIO controller has four GPIO pins which can be configurable as input or output. Modepin driver is a bridge between the peripheral driver and GPIO pins. It has set and get APIs for accessing GPIO pins, based on the device-tree entry of reset-gpio property in the peripheral driver, every pin can be configured as input/output and trigger GPIO pin. For more information please refer zynqMp TRM link: Link: https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf Chapter 2: Signals, Interfaces, and Pins Table 2-2: Clock, Reset, and Configuration Pins - PS_MODE Signed-off-by: Piyush Mehta --- Changes in v2: - Addressed review comments: Update commit message https://lore.kernel.org/linux-arm-kernel/20210615080553.2021061-2-piyush.mehta@xilinx.com/T/#mbd1fbda813e33b19397b350bde75747c92a0d7e1 https://lore.kernel.org/linux-arm-kernel/20210615080553.2021061-2-piyush.mehta@xilinx.com/T/#me82b1444ab3776162cdb0077dfc9256365c7e736 --- .../bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 41 ++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml diff --git a/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml new file mode 100644 index 0000000..39d78f8 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ZynqMP Mode Pin GPIO controller + +description: + PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin + GPIO controller with configurable from numbers of pins (from 0 to 3 per + PS_MODE). Every pin can be configured as input/output. + +maintainers: + - Piyush Mehta + +properties: + compatible: + const: xlnx,zynqmp-gpio-modepin + + gpio-controller: true + + "#gpio-cells": + const: 2 + +required: + - compatible + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; + +...