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Mon, 09 Aug 2021 23:14:01 -0700 (PDT) X-Google-Smtp-Source: ABdhPJxhBp7kqsbGZEA1dlKWoW0xLul7DAphDoiACSkpW5Vk2Une8bWIombRspvg8SL44s9TMrGitQ== X-Received: by 2002:a7b:c7d1:: with SMTP id z17mr2817569wmk.50.1628576041270; Mon, 09 Aug 2021 23:14:01 -0700 (PDT) Received: from gollum.fritz.box ([194.191.244.86]) by smtp.gmail.com with ESMTPSA id h11sm14676563wrq.64.2021.08.09.23.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Aug 2021 23:14:00 -0700 (PDT) From: Juerg Haefliger X-Google-Original-From: Juerg Haefliger To: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk Cc: linux-kernel@vger.kernel.org, Juerg Haefliger Subject: [PATCH] ARM: Fix instruction set selection for GCC 11 Date: Tue, 10 Aug 2021 08:13:50 +0200 Message-Id: <20210810061350.754134-1-juergh@canonical.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210809_231412_574463_407EE98F X-CRM114-Status: GOOD ( 17.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org GCC 11 on ARM now complains like the following when trying to determine if an arch is supported. Presumably because it enforces the default option '--with-float=hard' which GCC 10 didn't do? $ arm-linux-gnueabihf-gcc-11 -march=armv7-a -c -x c /dev/null cc1: error: ‘-mfloat-abi=hard’: selected architecture lacks an FPU Due to that, the kernel build system selects the wrong compiler options which throws errros like this during the build: /tmp/ccrHfZPj.s: Assembler messages: /tmp/ccrHfZPj.s:116: Error: selected processor does not support `dmb ish' in ARM mode /tmp/ccrHfZPj.s:150: Error: selected processor does not support `isb ' in ARM mode /tmp/ccrHfZPj.s:160: Error: selected processor does not support `mrrc p15,1,r4,r5,c14' in ARM mode /tmp/ccrHfZPj.s:245: Error: selected processor does not support `dmb ish' in ARM mode /tmp/ccrHfZPj.s:503: Error: selected processor does not support `dmb ish' in ARM mode /tmp/ccrHfZPj.s:527: Error: selected processor does not support `dmb ish' in ARM mode /tmp/ccrHfZPj.s:698: Error: selected processor does not support `dmb ish' in ARM mode /tmp/ccrHfZPj.s:731: Error: selected processor does not support `isb ' in ARM mode Fix that by adding '-msoft-float' to KBUILD_CFLAGS before the definition of the 'arch-$(CONFIG_CPU_)' instruction selection macros. Signed-off-by: Juerg Haefliger --- arch/arm/Makefile | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 173da685a52e..d21198833997 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -56,6 +56,9 @@ endif # KBUILD_CFLAGS += $(call cc-option,-fno-ipa-sra) +# Need -msoft-float for gcc 11 for the below instruction set selection +KBUILD_CFLAGS += -msoft-float + # This selects which instruction set is used. # Note that GCC does not numerically define an architecture version # macro, but instead defines a whole series of macros which makes @@ -125,7 +128,7 @@ AFLAGS_ISA :=$(CFLAGS_ISA) endif # Need -Uarm for gcc < 3.x -KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm +KBUILD_CFLAGS +=$(CFLAGS_ABI) $(CFLAGS_ISA) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -Uarm KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float CHECKFLAGS += -D__arm__