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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# # Copyright (c) 2021 Aspeed Technology Inc.
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/aspeed/espi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Aspeed eSPI Controller
+
+maintainers:
+ - Chia-Wei Wang <chiawei_wang@aspeedtech.com>
+ - Ryan Chen <ryan_chen@aspeedtech.com>
+
+description:
+ Aspeed eSPI controller implements a slave side eSPI endpoint device
+ supporting the four eSPI channels, namely peripheral, virtual wire,
+ out-of-band, and flash.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2500-espi
+ - aspeed,ast2600-espi
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+patternProperties:
+ "^espi-ctrl@[0-9a-f]+$":
+ type: object
+
+ description: Control of the four basic eSPI channels
+
+ properties:
+ compatible:
+ items:
+ - enum:
+ - aspeed,ast2500-espi-ctrl
+ - aspeed,ast2600-espi-ctrl
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ perif,memcyc-enable:
+ type: boolean
+ description: Enable memory cycle over eSPI peripheral channel
+
+ perif,memcyc-src-addr:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The Host side address to be decoded into the memory cycle over eSPI peripheral channel
+
+ perif,memcyc-size:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: The size of the memory region allocated for the memory cycle over eSPI peripheral channel
+ minimum: 65536
+
+ perif,dma-mode:
+ type: boolean
+ description: Enable DMA support for eSPI peripheral channel
+
+ oob,dma-mode:
+ type: boolean
+ description: Enable DMA support for eSPI out-of-band channel
+
+ oob,dma-tx-desc-num:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 2
+ maximum: 1023
+ description: The number of TX descriptors available for eSPI OOB DMA engine
+
+ oob,dma-rx-desc-num:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 2
+ maximum: 1023
+ description: The number of RX descriptors available for eSPI OOB DMA engine
+
+ flash,dma-mode:
+ type: boolean
+ description: Enable DMA support for eSPI flash channel
+
+ flash,safs-mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 0, 1, 2 ]
+ default: 0
+ description: Slave-Attached-Sharing-Flash mode, 0->Mix, 1->SW, 2->HW
+
+ dependencies:
+ perif,memcyc-src-addr: [ "perif,memcyc-enable" ]
+ perif,memcyc-size: [ "perif,memcyc-enable" ]
+ oob,dma-tx-desc-num: [ "oob,dma-mode" ]
+ oob,dma-rx-desc-num: [ "oob,dma-mode" ]
+
+ required:
+ - compatible
+ - interrupts
+ - clocks
+
+ "^espi-mmbi@[0-9a-f]+$":
+ type: object
+
+ description: Control of the PCH-BMC data exchange over eSPI peripheral memory cycle
+
+ properties:
+ compatible:
+ const: aspeed,ast2600-espi-mmbi
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - interrupts
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/ast2600-clock.h>
+
+ espi: espi@1e6ee000 {
+ compatible = "aspeed,ast2600-espi", "simple-mfd", "syscon";
+ reg = <0x1e6ee000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x1e6ee000 0x1000>;
+
+ espi_ctrl: espi-ctrl@0 {
+ compatible = "aspeed,ast2600-espi-ctrl";
+ reg = <0x0 0x800>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_ESPICLK>;
+ };
+
+ espi_mmbi: espi-mmbi@800 {
+ compatible = "aspeed,ast2600-espi-mmbi";
+ reg = <0x800 0x50>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
Add dt-bindings for Aspeed eSPI controller Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> --- .../devicetree/bindings/soc/aspeed/espi.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/aspeed/espi.yaml