diff mbox series

arm64: dts: visconti: Add PCIe host controller support for TMPV7708 SoC

Message ID 20210907042500.1525771-1-nobuhiro1.iwamatsu@toshiba.co.jp (mailing list archive)
State New, archived
Headers show
Series arm64: dts: visconti: Add PCIe host controller support for TMPV7708 SoC | expand

Commit Message

Nobuhiro Iwamatsu Sept. 7, 2021, 4:25 a.m. UTC 
Add PCIe node and fixed clock for PCIe in TMPV7708's dtsi,
and tmpv7708-rm-mbrc boards's dts.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
---
 .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts     |  6 +++
 arch/arm64/boot/dts/toshiba/tmpv7708.dtsi     | 52 +++++++++++++++++++
 2 files changed, 58 insertions(+)

Comments

Nobuhiro Iwamatsu Sept. 9, 2021, 12:34 a.m. UTC | #1 
Hi,

On Tue, Sep 07, 2021 at 01:25:00PM +0900, Nobuhiro Iwamatsu wrote:
> Add PCIe node and fixed clock for PCIe in TMPV7708's dtsi,
> and tmpv7708-rm-mbrc boards's dts.
> 
> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
> ---
>  .../boot/dts/toshiba/tmpv7708-rm-mbrc.dts     |  6 +++
>  arch/arm64/boot/dts/toshiba/tmpv7708.dtsi     | 52 +++++++++++++++++++
>  2 files changed, 58 insertions(+)
> 

Applied, thanks.

Best regards,
  Nobuhiro

> diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> index 29a4d9fc1e47..9375b0faeea2 100644
> --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
> @@ -76,3 +76,9 @@ &pwm_mux {
>  &pwm {
>  	status = "okay";
>  };
> +
> +&pcie {
> +	status = "okay";
> +	clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
> +	clock-names = "ref", "core", "aux";
> +};
> diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> index 4b4231ff43cf..5db9a012d6fc 100644
> --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
> @@ -134,6 +134,13 @@ uart_clk: uart-clk {
>  		#clock-cells = <0>;
>  	};
>  
> +	clk25mhz: clk25mhz {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;
> +		clock-output-names = "clk25mhz";
> +	};
> +
>  	clk125mhz: clk125mhz {
>  		compatible = "fixed-clock";
>  		clock-frequency = <125000000>;
> @@ -148,6 +155,20 @@ clk300mhz: clk300mhz {
>  		clock-output-names = "clk300mhz";
>  	};
>  
> +	clk600mhz: clk600mhz {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <600000000>;
> +		clock-output-names = "clk600mhz";
> +	};
> +
> +	extclk100mhz: extclk100mhz {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "extclk100mhz";
> +	};
> +
>  	wdt_clk: wdt-clk {
>  		compatible = "fixed-clock";
>  		clock-frequency = <150000000>;
> @@ -441,6 +462,37 @@ pwm: pwm@241c0000 {
>  			#pwm-cells = <2>;
>  			status = "disabled";
>  		};
> +
> +		pcie: pcie@28400000 {
> +			compatible = "toshiba,visconti-pcie";
> +			reg = <0x0 0x28400000 0x0 0x00400000>,
> +			      <0x0 0x70000000 0x0 0x10000000>,
> +			      <0x0 0x28050000 0x0 0x00010000>,
> +			      <0x0 0x24200000 0x0 0x00002000>,
> +			      <0x0 0x24162000 0x0 0x00001000>;
> +			reg-names  = "dbi", "config", "ulreg", "smu", "mpu";
> +			device_type = "pci";
> +			bus-range = <0x00 0xff>;
> +			num-lanes = <2>;
> +			num-viewport = <8>;
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +			#interrupt-cells = <1>;
> +			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
> +				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
> +			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "msi", "intr";
> +			interrupt-map-mask = <0 0 0 7>;
> +			interrupt-map =
> +				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
> +				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
> +			max-link-speed = <2>;
> +			status = "disabled";
> +		};
>  	};
>  };
>  
> -- 
> 2.32.0
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
index 29a4d9fc1e47..9375b0faeea2 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts
@@ -76,3 +76,9 @@  &pwm_mux {
 &pwm {
 	status = "okay";
 };
+
+&pcie {
+	status = "okay";
+	clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>;
+	clock-names = "ref", "core", "aux";
+};
diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
index 4b4231ff43cf..5db9a012d6fc 100644
--- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
+++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi
@@ -134,6 +134,13 @@  uart_clk: uart-clk {
 		#clock-cells = <0>;
 	};
 
+	clk25mhz: clk25mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <25000000>;
+		clock-output-names = "clk25mhz";
+	};
+
 	clk125mhz: clk125mhz {
 		compatible = "fixed-clock";
 		clock-frequency = <125000000>;
@@ -148,6 +155,20 @@  clk300mhz: clk300mhz {
 		clock-output-names = "clk300mhz";
 	};
 
+	clk600mhz: clk600mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <600000000>;
+		clock-output-names = "clk600mhz";
+	};
+
+	extclk100mhz: extclk100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "extclk100mhz";
+	};
+
 	wdt_clk: wdt-clk {
 		compatible = "fixed-clock";
 		clock-frequency = <150000000>;
@@ -441,6 +462,37 @@  pwm: pwm@241c0000 {
 			#pwm-cells = <2>;
 			status = "disabled";
 		};
+
+		pcie: pcie@28400000 {
+			compatible = "toshiba,visconti-pcie";
+			reg = <0x0 0x28400000 0x0 0x00400000>,
+			      <0x0 0x70000000 0x0 0x10000000>,
+			      <0x0 0x28050000 0x0 0x00010000>,
+			      <0x0 0x24200000 0x0 0x00002000>,
+			      <0x0 0x24162000 0x0 0x00001000>;
+			reg-names  = "dbi", "config", "ulreg", "smu", "mpu";
+			device_type = "pci";
+			bus-range = <0x00 0xff>;
+			num-lanes = <2>;
+			num-viewport = <8>;
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			ranges = <0x81000000 0 0x40000000 0 0x40000000 0 0x00010000
+				  0x82000000 0 0x50000000 0 0x50000000 0 0x20000000>;
+			interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "msi", "intr";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map =
+				<0 0 0 1 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+				 0 0 0 2 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+				 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH
+				 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
+			max-link-speed = <2>;
+			status = "disabled";
+		};
 	};
 };