diff mbox series

net: stmmac: allow CSR clock of 300MHz

Message ID 20210910195535.12533-1-jesper.nilsson@axis.com (mailing list archive)
State New, archived
Headers show
Series net: stmmac: allow CSR clock of 300MHz | expand

Commit Message

Jesper Nilsson Sept. 10, 2021, 7:55 p.m. UTC
The Synopsys Ethernet IP uses the CSR clock as a base clock for MDC.
The divisor used is set in the MAC_MDIO_Address register field CR
(Clock Rate)

The divisor is there to change the CSR clock into a clock that falls
below the IEEE 802.3 specified max frequency of 2.5MHz.

If the CSR clock is 300MHz, the code falls back to using the reset
value in the MAC_MDIO_Address register, as described in the comment
above this code.

However, 300MHz is actually an allowed value and the proper divider
can be estimated quite easily (it's just 1Hz difference!)

A CSR frequency of 300MHz with the maximum clock rate value of 0x5
(STMMAC_CSR_250_300M, a divisor of 124) gives somewhere around
~2.42MHz which is below the IEEE 802.3 specified maximum.

For the ARTPEC-8 SoC, the CSR clock is this problematic 300MHz,
and unfortunately, the reset-value of the MAC_MDIO_Address CR field
is 0x0.

This leads to a clock rate of zero and a divisor of 42, and gives an
MDC frequency of ~7.14MHz.

Allow CSR clock of 300MHz by making the comparison inclusive.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

patchwork-bot+netdevbpf@kernel.org Sept. 11, 2021, 9:30 a.m. UTC | #1
Hello:

This patch was applied to netdev/net.git (refs/heads/master):

On Fri, 10 Sep 2021 21:55:34 +0200 you wrote:
> The Synopsys Ethernet IP uses the CSR clock as a base clock for MDC.
> The divisor used is set in the MAC_MDIO_Address register field CR
> (Clock Rate)
> 
> The divisor is there to change the CSR clock into a clock that falls
> below the IEEE 802.3 specified max frequency of 2.5MHz.
> 
> [...]

Here is the summary with links:
  - net: stmmac: allow CSR clock of 300MHz
    https://git.kernel.org/netdev/net/c/08dad2f4d541

You are awesome, thank you!
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diff mbox series

Patch

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index ece02b35a6ce..6560d9f24715 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -309,7 +309,7 @@  static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 			priv->clk_csr = STMMAC_CSR_100_150M;
 		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 			priv->clk_csr = STMMAC_CSR_150_250M;
-		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
+		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 			priv->clk_csr = STMMAC_CSR_250_300M;
 	}