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[180.9.58.106]) by smtp.googlemail.com with ESMTPSA id b5sm1193140pjq.2.2021.09.14.03.04.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Sep 2021 03:04:24 -0700 (PDT) From: Daniel Palmer To: devicetree@vger.kernel.org, robh+dt@kernel.org, maz@kernel.org, tglx@linutronix.de Cc: linux-arm-kernel@lists.infradead.org, romain.perier@gmail.com, Daniel Palmer Subject: [PATCH 1/3] dt-bindings: interrupt-controller: Add SigmaStar SSD20xD gpi Date: Tue, 14 Sep 2021 19:04:13 +0900 Message-Id: <20210914100415.1549208-2-daniel@0x0f.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210914100415.1549208-1-daniel@0x0f.com> References: <20210914100415.1549208-1-daniel@0x0f.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210914_030425_740587_34627F76 X-CRM114-Status: GOOD ( 17.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add a binding description for the SigmaStar GPIO interrupt controller, gpi, found on the SSD201 and SSD202D. Signed-off-by: Daniel Palmer Reviewed-by: Rob Herring --- .../sstar,ssd20xd-gpi.yaml | 53 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml b/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml new file mode 100644 index 000000000000..1f7e6c5fef52 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sstar,ssd20xd-gpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SigmaStar GPIO Interrupt Controller + +maintainers: + - Daniel Palmer + +description: |+ + Newer SigmaStar SoCs from the SSD201/SSD202D have an extra + interrupt controller that is just for handling interrupts + on GPIOs and then routing a single interrupt to the peripheral + interrupt controller instead of only having a few interrupt + capable GPIOs that are routed directly to the peripheral + interrupt controller like older SoCs. + +properties: + compatible: + const: sstar,ssd20xd-gpi + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + interrupt-controller@207a00 { + compatible = "sstar,ssd20xd-gpi"; + reg = <0x207a00 0x200>; + #interrupt-cells = <2>; + interrupt-controller; + interrupts-extended = <&intc_irq GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + }; +... diff --git a/MAINTAINERS b/MAINTAINERS index eeb4c70b3d5b..3004c0f735b6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2243,6 +2243,7 @@ T: git git://github.com/linux-chenxing/linux.git F: Documentation/devicetree/bindings/arm/mstar/* F: Documentation/devicetree/bindings/clock/mstar,msc313-mpll.yaml F: Documentation/devicetree/bindings/gpio/mstar,msc313-gpio.yaml +F: Documentation/devicetree/bindings/interrupt-controller/sstar,ssd20xd-gpi.yaml F: arch/arm/boot/dts/mstar-* F: arch/arm/mach-mstar/ F: drivers/clk/mstar/