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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=B0jnz+rbECpcz7uKTBggzSG6EdZ04xMucQGoL9FLFQA=; b=l/q5ALx/nf031cr6QmfG9zqGwVNOu2gXY0EY87RAfegDE/FKH14c20e4mDu+ND/QKX 6zOhnVBgt9kgYY5Uibq3/BLNGcFSqGgS8RD93XKQ2D6pOZZwnvVvM9VZv3lrG7NVYdwD ft4i4BDEuCiDhMyBDTq2PH16uIGnIDBH84xJHxhuoM6qusLKzWXOkRURrwd/afkCwJWr F0V3qnaPjh7x3ZXCDqK14qXf27/cEFOMR907FHw7ytMfkCo6imjO8M4xHhnQWb61h3I/ MxRciZQiibkTLQJClvOHXLBXXyUeLJrShskOoLUidL47YCm3wyorxurAedc3ZV7qLlHe vhPA== X-Gm-Message-State: AOAM531qDewzbawGR3oisZ8LMw3w+gj5rFDrz4QByiS7qgLN1/rhawj6 RAz2sA/an0GUvsONd+gnDDV+L3k= X-Google-Smtp-Source: ABdhPJw9oa2zDH0i7VoMgV2RTtc3BLkWLUU13wXYTBWVi1ma3glWayzgj0/DRR/MRsmeajoP3/2pqrI= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:931e:1e8c:a36f:9255]) (user=pcc job=sendgmr) by 2002:a25:d6cf:: with SMTP id n198mr1845202ybg.535.1631732621722; Wed, 15 Sep 2021 12:03:41 -0700 (PDT) Date: Wed, 15 Sep 2021 12:03:35 -0700 Message-Id: <20210915190336.398390-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.33.0.309.g3052b89438-goog Subject: [PATCH v3 1/2] arm64: add an MTE support check to the top of mte_thread_switch() From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210915_120346_541042_C252DDAD X-CRM114-Status: GOOD ( 15.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This lets us avoid doing unnecessary work on hardware that does not support MTE, and will allow us to freely use MTE instructions in the code called by mte_thread_switch(). Since this would mean that we do a redundant check in mte_check_tfsr_el1(), remove it and add two checks now required in its callers. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/I02fd000d1ef2c86c7d2952a7f099b254ec227a5d --- v3: - remove check from mte_check_tfsr_el1() arch/arm64/include/asm/mte.h | 6 ++++++ arch/arm64/kernel/mte.c | 10 ++++------ 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h index 3f93b9e0b339..02511650cffe 100644 --- a/arch/arm64/include/asm/mte.h +++ b/arch/arm64/include/asm/mte.h @@ -99,11 +99,17 @@ void mte_check_tfsr_el1(void); static inline void mte_check_tfsr_entry(void) { + if (!system_supports_mte()) + return; + mte_check_tfsr_el1(); } static inline void mte_check_tfsr_exit(void) { + if (!system_supports_mte()) + return; + /* * The asynchronous faults are sync'ed automatically with * TFSR_EL1 on kernel entry but for exit an explicit dsb() diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c index 9d314a3bad3b..e5e801bc5312 100644 --- a/arch/arm64/kernel/mte.c +++ b/arch/arm64/kernel/mte.c @@ -142,12 +142,7 @@ void mte_enable_kernel_async(void) #ifdef CONFIG_KASAN_HW_TAGS void mte_check_tfsr_el1(void) { - u64 tfsr_el1; - - if (!system_supports_mte()) - return; - - tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1); + u64 tfsr_el1 = read_sysreg_s(SYS_TFSR_EL1); if (unlikely(tfsr_el1 & SYS_TFSR_EL1_TF1)) { /* @@ -199,6 +194,9 @@ void mte_thread_init_user(void) void mte_thread_switch(struct task_struct *next) { + if (!system_supports_mte()) + return; + mte_update_sctlr_user(next); /*