| Message ID | 20210921134121.2423546-18-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Self-hosted trace related errata workarounds | expand |
On 9/21/21 7:11 PM, Suzuki K Poulose wrote: > Add Kconfig entries for the errata workarounds for TRBE writing > to an out-of-range address. > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > Documentation/arm64/silicon-errata.rst | 4 +++ > arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ > 2 files changed, 43 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 569a92411dcd..5342e895fb60 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -96,6 +96,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1349291 | N/A | > @@ -106,6 +108,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #841119,826419 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 0764774e12bb..611ae02aabbd 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -736,6 +736,45 @@ config ARM64_ERRATUM_2067961 > > If unsure, say Y. > > +config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > + bool > + > +config ARM64_ERRATUM_2253138 > + bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" > + depends on CORESIGHT_TRBE > + default y > + select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > + help > + This option adds the workaround for ARM Neoverse-N2 erratum 2253138. > + > + Affected Neoverse-N2 cores might write to an out-of-range address, not reserved > + for TRBE. Under some conditions, the TRBE might generate a write to the next > + virtually addressed page following the last page of the TRBE address space > + (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. > + > + We work around this in the driver by, always making sure that there is a > + page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. > + > + If unsure, say Y. > + > +config ARM64_ERRATUM_2224489 > + bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range" > + depends on CORESIGHT_TRBE > + default y > + select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > + help > + This option adds the workaround for ARM Cortex-A710 erratum 2224489. > + > + Affected Cortex-A710 cores might write to an out-of-range address, not reserved > + for TRBE. Under some conditions, the TRBE might generate a write to the next > + virtually addressed page following the last page of the TRBE address space > + (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. > + > + We work around this in the driver by, always making sure that there is a > + page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y >
On Tue, Sep 21, 2021 at 02:41:21PM +0100, Suzuki K Poulose wrote: > Add Kconfig entries for the errata workarounds for TRBE writing > to an out-of-range address. > > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Leo Yan <leo.yan@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 569a92411dcd..5342e895fb60 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -96,6 +96,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | @@ -106,6 +108,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 0764774e12bb..611ae02aabbd 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -736,6 +736,45 @@ config ARM64_ERRATUM_2067961 If unsure, say Y. +config ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE + bool + +config ARM64_ERRATUM_2253138 + bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range" + depends on CORESIGHT_TRBE + default y + select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE + help + This option adds the workaround for ARM Neoverse-N2 erratum 2253138. + + Affected Neoverse-N2 cores might write to an out-of-range address, not reserved + for TRBE. Under some conditions, the TRBE might generate a write to the next + virtually addressed page following the last page of the TRBE address space + (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. + + We work around this in the driver by, always making sure that there is a + page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. + + If unsure, say Y. + +config ARM64_ERRATUM_2224489 + bool "Cortex-A710: 2224489: workaround TRBE writing to address out-of-range" + depends on CORESIGHT_TRBE + default y + select ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE + help + This option adds the workaround for ARM Cortex-A710 erratum 2224489. + + Affected Cortex-A710 cores might write to an out-of-range address, not reserved + for TRBE. Under some conditions, the TRBE might generate a write to the next + virtually addressed page following the last page of the TRBE address space + (i.e, the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base. + + We work around this in the driver by, always making sure that there is a + page beyond the TRBLIMITR_EL1.LIMIT, within the space allowed for the TRBE. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y
Add Kconfig entries for the errata workarounds for TRBE writing to an out-of-range address. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Anshuman Khandual <anshuman.khandual@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> --- Documentation/arm64/silicon-errata.rst | 4 +++ arch/arm64/Kconfig | 39 ++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)