diff mbox series

[3/5] ARM: dts: imx6sll: fixup of operating points

Message ID 20210923201238.2516844-4-andreas@kemnade.info (mailing list archive)
State New, archived
Headers show
Series ARM: dts: imx6sl / imx6sll: dtbs_check errors | expand

Commit Message

Andreas Kemnade Sept. 23, 2021, 8:12 p.m. UTC 
Make operating point definitions comply with binding
specifications.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
---
 arch/arm/boot/dts/imx6sll.dtsi | 22 ++++++++++------------
 1 file changed, 10 insertions(+), 12 deletions(-)

Comments

Krzysztof Kozlowski Sept. 24, 2021, 8:18 a.m. UTC | #1 
On 23/09/2021 22:12, Andreas Kemnade wrote:
> Make operating point definitions comply with binding
> specifications.
> 
> Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
> ---
>  arch/arm/boot/dts/imx6sll.dtsi | 22 ++++++++++------------
>  1 file changed, 10 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
> index 04f8d637a501..0f148f498374 100644
> --- a/arch/arm/boot/dts/imx6sll.dtsi
> +++ b/arch/arm/boot/dts/imx6sll.dtsi
> @@ -51,20 +51,18 @@ cpu0: cpu@0 {
>  			device_type = "cpu";
>  			reg = <0>;
>  			next-level-cache = <&L2>;
> -			operating-points = <
> +			operating-points =
>  				/* kHz    uV */
> -				996000  1275000
> -				792000  1175000
> -				396000  1075000
> -				198000	975000
> -			>;
> -			fsl,soc-operating-points = <
> +				<996000  1275000>,
> +				<792000  1175000>,
> +				<396000  1075000>,
> +				<198000	975000>;

Please align this line, so I guess double space.

With the change:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 04f8d637a501..0f148f498374 100644
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -51,20 +51,18 @@  cpu0: cpu@0 {
 			device_type = "cpu";
 			reg = <0>;
 			next-level-cache = <&L2>;
-			operating-points = <
+			operating-points =
 				/* kHz    uV */
-				996000  1275000
-				792000  1175000
-				396000  1075000
-				198000	975000
-			>;
-			fsl,soc-operating-points = <
+				<996000  1275000>,
+				<792000  1175000>,
+				<396000  1075000>,
+				<198000	975000>;
+			fsl,soc-operating-points =
 				/* ARM kHz      SOC-PU uV */
-				996000          1175000
-				792000          1175000
-				396000          1175000
-				198000		1175000
-			>;
+				<996000         1175000>,
+				<792000         1175000>,
+				<396000         1175000>,
+				<198000		1175000>;
 			clock-latency = <61036>; /* two CLK32 periods */
 			#cooling-cells = <2>;
 			clocks = <&clks IMX6SLL_CLK_ARM>,