From patchwork Fri Sep 24 16:28:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 12515977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 98D74C433EF for ; Fri, 24 Sep 2021 16:31:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 65A4F61212 for ; Fri, 24 Sep 2021 16:31:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 65A4F61212 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=FcV7ez7HUUMWBoBX/NxhvMPPxQpnFflL+74+Hpdqg+4=; b=oWoJKWNF4B1uG4 Z+cSxg9OeAanSWNNiEot3RYo+wKMEibeONZ4cDjeNsKgxC74GEH1U8WN1R2ub1fHDx1fDeqhXDQVc eCR8JrFI5kRBp9sGdfml9xFAl9Vm2ptt6d55Pk4NYuH3g79IaT2TJhXqMpPRxiveArsRiFStj6rLP wh7TvIeo+os9gHgVGuJ2wsmpptAo/RMo92nU8cKItmnFaqRbUxIXQWlQ8PoYhSn53mImiU8ziumni 53I7qCvuYk8g6HKcanRYDK2jl+tEGr4znXNuoIEHdBSSro1AR+fH2GNsYAr/xIbhS795hP30VZXue 7JoBRHWIQGsO4i4L8Zdg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTo47-00F3ju-1q; Fri, 24 Sep 2021 16:28:47 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mTo3t-00F3hJ-Gg for linux-arm-kernel@lists.infradead.org; Fri, 24 Sep 2021 16:28:35 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1632500913; x=1664036913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=C/MuNZIFL8T6FfSyf5qyBIEBQRoAmkVs4MN5QIDFeIo=; b=rKDYD1TEU/oV6JfBUvQp+510m/SZlYttUeej//qe3WhntjW8XaVGxAdt Bm120g4CcJNspXqmfa5fUo2WVLSvfS/jXQTdRQDhdx0CEBmv8MXBpPZcy 6wxjcdxHGfMA17y03BnxSCbG8DMj0+bHgii82wBdoFEp5CuxzAV1KT/FF kcZ1Iwfy1rjMfRyNMaE9FXypZMuStZJCKEFSGH7Q0DQv1bb5hM5NH6gfT MaWBYVB7dQIeJlx41bUW4tPtFpp1sDEm9jlgQRctjk8yUFNo/oE34wbBv hukGbpIe/tHErEXDpWUAV6mBCf9uXLrHYkKmK8htJQrbm9o+uPAiMj90g g==; IronPort-SDR: V9BqGbrbfxifDT6NbeIOgv9iUPrUlCO51A+IAxQoda+jCa8OLcvlpkGngnNSi6OaNfAHUp+tiQ IGjioA73S4etldHu6uUBE2cukaZPZdNWpKbOguxhJEUU9Vfko7TU7iIZbHu3herDqdrQd4KF2+ 7K0KV/rLs38eko+KeUlVXY2OQ0DCu/rj4FiYlreqX4imKyPlB6XFWLWB9BYe2RvP5aSjoQtXbq F8t3yt63IF6f/HROMizqMDx8s+X3BpK3VIpdqmYfy9W/CPzyQ1Yo1JIbqU3TQck6BJFLNMKJVf cyIUQtiQ1Ixm4FJtAEoiJ80n X-IronPort-AV: E=Sophos;i="5.85,320,1624345200"; d="scan'208";a="137875637" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Sep 2021 09:28:31 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Fri, 24 Sep 2021 09:28:31 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Fri, 24 Sep 2021 09:28:28 -0700 From: Claudiu Beznea To: , , CC: , , , Claudiu Beznea , Rob Herring Subject: [PATCH v3 1/2] dt-bindings: microchip,eic: add bindings Date: Fri, 24 Sep 2021 19:28:16 +0300 Message-ID: <20210924162817.2135056-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210924162817.2135056-1-claudiu.beznea@microchip.com> References: <20210924162817.2135056-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210924_092833_587402_EDFFAA4C X-CRM114-Status: GOOD ( 13.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add DT bindings for Microchip External Interrupt Controller. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring --- .../interrupt-controller/microchip,eic.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml new file mode 100644 index 000000000000..917a35e97b7a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/microchip,eic.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/microchip,eic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip External Interrupt Controller + +maintainers: + - Claudiu Beznea + +description: + This interrupt controller is found in Microchip SoCs (SAMA7G5) and provides + support for handling up to 2 external interrupt lines. + +properties: + compatible: + enum: + - microchip,sama7g5-eic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + description: + The first cell is the input IRQ number (between 0 and 1), the second cell + is the trigger type as defined in interrupt.txt present in this directory. + + interrupts: + description: | + Contains the GIC SPI IRQs mapped to the external interrupt lines. They + should be specified sequentially from output 0 to output 1. + minItems: 2 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: pclk + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + eic: interrupt-controller@e1628000 { + compatible = "microchip,sama7g5-eic"; + reg = <0xe1628000 0x100>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = , + ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; + clock-names = "pclk"; + }; + +...