From patchwork Wed Sep 29 19:45:24 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Collingbourne X-Patchwork-Id: 12526519 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AB8CC433EF for ; Wed, 29 Sep 2021 19:47:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 186AC61462 for ; Wed, 29 Sep 2021 19:47:45 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 186AC61462 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Mime-Version: Message-Id:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To: References:List-Owner; bh=fqstC68bfpDSevqV4ZX+wJ66vld+KS+5Dmc5tbOULU0=; b=UHO L4gHd70gRNoVYLzVhwWZz/XB/p86wHLGx5xaXm5/UAC2AC6Fw7B0wlnnfnrN/a0i7fq85+iHHU3z8 9XXX8Jb5/SmyywCBmFUaCc3m1vxtdNg90jmj9123Efz/PvLhto+84oIMvRnlnGJr6k6lqMRONMkov 5wEwxDFYX8vRqaVlNILfapGPSOM2GdH5JfY7IxJU9zGcfqfWIoFQ4Ki0Fch8ydoe7swbhJDnHioq2 FKR3dbeKAsJtXrHDNsAYRbkp4N97LHxsTijmixX7WIQKStzd/s4ZgX/ab9D9MxPeqUbzvC5xqxWcy o2pAkHrpXWZ5DGP9Pxw3xXhazr04k0w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mVfWR-00CCuM-Te; Wed, 29 Sep 2021 19:45:44 +0000 Received: from mail-qv1-xf4a.google.com ([2607:f8b0:4864:20::f4a]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mVfWN-00CCsq-HU for linux-arm-kernel@lists.infradead.org; Wed, 29 Sep 2021 19:45:41 +0000 Received: by mail-qv1-xf4a.google.com with SMTP id e6-20020a0cb446000000b0037eeb9851dfso8751928qvf.17 for ; Wed, 29 Sep 2021 12:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=date:message-id:mime-version:subject:from:to:cc; bh=e3s0jiPkKfhJ+e4Xt2U4NuXZviRnyp3aRr1WljrO230=; b=UAj2NTERYG3V9zoqrtlrmlFoAFIoD1mO1SdhBSSuPSvAfs25KPJrtEH7fUojBvzSdK dlUw7L1Y4mq9fO1EOn3bybBh2fKNymh5WVaJ73eA0nNovMhPQ3fu6kIMgfcgVzGRIwIr QMDWIE8ADh4nI2krCG9pzXTF4UYl/6k25NxFUb+Vw3z0Osk/CeO/htCoTWtT3hr4f9qy DsYOyXLmUQe/NW4hozX9ayG1u8fOGOJ1kFIcQMf/yddxP2ArEpAUVnYUqUr5Ir7jXrPv SC+HJpK/Vr67DFA2cwmBB2DjpjKc7d+OmAlxCxKoggusV6HLY7HKUNm8/o6iA9AsYvxr tSZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=e3s0jiPkKfhJ+e4Xt2U4NuXZviRnyp3aRr1WljrO230=; b=H4+h2btMuShzGkR+HH2BfJxPenXOWsGGnOOxtTVoHXfUeuTIfstSl8IxPYLQZtOL4e jMnGCc0SogzwPhPaRKFdr8nYor27cdeHnGIk8Z6OAXg5Ji6Rx+Zbr3rCgBMQLt031UPu u1nFweEB5NCPd73qa12hfW77HA/tg3874V3VQUPGysNa6ghEGG5/utFLW3K9+MTYDrTV 6kOCQ5Hd2tuLVMUtWA26O0JPE5OqeFHxFU/3MrFz5P45iRpo/Rr/Ep3r2cGHWNaj4mU4 6r+ySw8B7cDAtiEI2qgbcRczabuKT6h4Skix+C40Hf9BbcG5qIZ+s/rlZ1a36Cw2cwKq xSKw== X-Gm-Message-State: AOAM530B1isY+S/9KxAhfVZjXy+bpWt08g1qVvDD0M4sFG2lydEgJlLF njWlV7YtZI0urDqB6izD8CTwbrc= X-Google-Smtp-Source: ABdhPJybs1uqXtiJuzpDcQff6ynKdFm1hbddmPI4paV37Nn9j/lB/nFHRl+hGKeWlyDYJoshLzhC1uQ= X-Received: from pcc-desktop.svl.corp.google.com ([2620:15c:2ce:200:4b75:60c:bf4:4a60]) (user=pcc job=sendgmr) by 2002:a05:6214:122e:: with SMTP id p14mr103617qvv.57.1632944737202; Wed, 29 Sep 2021 12:45:37 -0700 (PDT) Date: Wed, 29 Sep 2021 12:45:24 -0700 Message-Id: <20210929194525.3252555-1-pcc@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.33.0.800.g4c38ced690-goog Subject: [PATCH] arm64: mte: avoid clearing PSTATE.TCO on entry unless necessary From: Peter Collingbourne To: Catalin Marinas , Vincenzo Frascino , Will Deacon , Andrey Konovalov Cc: Peter Collingbourne , Evgenii Stepanov , linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210929_124539_610257_5C2F4348 X-CRM114-Status: GOOD ( 14.27 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On some microarchitectures, clearing PSTATE.TCO is expensive. Clearing TCO is only necessary if in-kernel MTE is enabled, or if MTE is enabled in the userspace process in synchronous (or, soon, asymmetric) mode, because we do not report uaccess faults to userspace in none or asynchronous modes. Therefore, adjust the kernel entry code to clear TCO only if necessary. Signed-off-by: Peter Collingbourne Link: https://linux-review.googlesource.com/id/I52d82a580bd0500d420be501af2c35fa8c90729e --- arch/arm64/kernel/entry.S | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 2f69ae43941d..85ead6bbb38e 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -269,7 +269,28 @@ alternative_else_nop_endif .else add x21, sp, #PT_REGS_SIZE get_current_task tsk + ldr x0, [tsk, THREAD_SCTLR_USER] .endif /* \el == 0 */ + + /* + * Re-enable tag checking (TCO set on exception entry). This is only + * necessary if MTE is enabled in either the kernel or the userspace + * task in synchronous mode. With MTE disabled in the kernel and + * disabled or asynchronous in userspace, tag check faults (including in + * uaccesses) are not reported, therefore there is no need to re-enable + * checking. This is beneficial on microarchitectures where re-enabling + * TCO is expensive. + */ +#ifdef CONFIG_ARM64_MTE +alternative_cb kasan_hw_tags_enable + tbz x0, #SCTLR_EL1_TCF0_SHIFT, 1f +alternative_cb_end +alternative_if ARM64_MTE + SET_PSTATE_TCO(0) +alternative_else_nop_endif +1: +#endif + mrs x22, elr_el1 mrs x23, spsr_el1 stp lr, x21, [sp, #S_LR] @@ -308,13 +329,6 @@ alternative_if ARM64_HAS_IRQ_PRIO_MASKING msr_s SYS_ICC_PMR_EL1, x20 alternative_else_nop_endif - /* Re-enable tag checking (TCO set on exception entry) */ -#ifdef CONFIG_ARM64_MTE -alternative_if ARM64_MTE - SET_PSTATE_TCO(0) -alternative_else_nop_endif -#endif - /* * Registers that may be useful after this macro is invoked: *