[v3,4/5] dt-bindings: clock: Document Exynos850 CMU bindings

Commit Message

Sam Protsenko Oct. 8, 2021, 3:43 p.m. UTC

Provide dt-schema documentation for Exynos850 SoC clock controller.

Signed-off-by: Sam Protsenko <[e-mail]>
Reviewed-by: Krzysztof Kozlowski <[e-mail]>
Acked-by: Chanwoo Choi <[e-mail]>
---
Changes in v3:
  -  Added R-b tag by Krzysztof Kozlowski

Changes in v2:
  - Dropped OSCCLK node declaration example
  - Dropped UART node declaration example
  - Added Ack tag by Chanwoo Choi

 .../clock/samsung,exynos850-clock.yaml        | 185 ++++++++++++++++++
 1 file changed, 185 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

Comments

Sylwester Nawrocki Oct. 9, 2021, 8:40 p.m. UTC | #1

On 08.10.2021 17:43, Sam Protsenko wrote:
> Provide dt-schema documentation for Exynos850 SoC clock controller.
> 
> Signed-off-by: Sam Protsenko <[e-mail]>
> Reviewed-by: Krzysztof Kozlowski <[e-mail]>
> Acked-by: Chanwoo Choi <[e-mail]>

> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> new file mode 100644
> index 000000000000..79202e6e6402
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -0,0 +1,185 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos850 SoC clock controller
> +
> +maintainers:
> +  - Sam Protsenko <[e-mail]>
> +  - Chanwoo Choi <[e-mail]>
> +  - Krzysztof Kozlowski <[e-mail]>
> +  - Sylwester Nawrocki <[e-mail]>
> +  - Tomasz Figa <[e-mail]>
> +
> +description: |
> +  Exynos850 clock controller is comprised of several CMU units, generating
> +  clocks for different domains. Those CMU units are modeled as separate device
> +  tree nodes, and might depend on each other. Root clocks in that clock tree are
> +  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
> +  clocks must be defined as fixed-rate clocks in dts.
> +
> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> +
> +  Each clock is assigned an identifier and client nodes can use this identifier
> +  to specify the clock which they consume. All clocks that available for usage

s/All clocks that available/All clocks available ?
No need to resend, I can amend it when applying.

Sam Protsenko Oct. 11, 2021, 10:13 a.m. UTC | #2

On Sat, 9 Oct 2021 at 23:41, Sylwester Nawrocki <[e-mail]> wrote:
>
> On 08.10.2021 17:43, Sam Protsenko wrote:
> > Provide dt-schema documentation for Exynos850 SoC clock controller.
> >
> > Signed-off-by: Sam Protsenko <[e-mail]>
> > Reviewed-by: Krzysztof Kozlowski <[e-mail]>
> > Acked-by: Chanwoo Choi <[e-mail]>
>
> > diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> > new file mode 100644
> > index 000000000000..79202e6e6402
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> > @@ -0,0 +1,185 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung Exynos850 SoC clock controller
> > +
> > +maintainers:
> > +  - Sam Protsenko <[e-mail]>
> > +  - Chanwoo Choi <[e-mail]>
> > +  - Krzysztof Kozlowski <[e-mail]>
> > +  - Sylwester Nawrocki <[e-mail]>
> > +  - Tomasz Figa <[e-mail]>
> > +
> > +description: |
> > +  Exynos850 clock controller is comprised of several CMU units, generating
> > +  clocks for different domains. Those CMU units are modeled as separate device
> > +  tree nodes, and might depend on each other. Root clocks in that clock tree are
> > +  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
> > +  clocks must be defined as fixed-rate clocks in dts.
> > +
> > +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> > +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> > +
> > +  Each clock is assigned an identifier and client nodes can use this identifier
> > +  to specify the clock which they consume. All clocks that available for usage
>
> s/All clocks that available/All clocks available ?
> No need to resend, I can amend it when applying.
>

Yeah, not a native speaker, I tend to do such mistakes sometimes :)
Please fix when applying.

Btw, I can see that you already applied 3 out of 5 patches from this
patch series here: [1]. Can you please also apply the rest, or is
there any outstanding comments that I missed?

[1] https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git/log/?h=for-v5.16/next

Sylwester Nawrocki/Kernel \(PLT\) /SRPOL/Staff Engineer/Samsung Electronics Oct. 11, 2021, 10:42 a.m. UTC | #3

On 11.10.2021 12:13, Sam Protsenko wrote:
> On Sat, 9 Oct 2021 at 23:41, Sylwester Nawrocki <[e-mail]> wrote:
>>
>> On 08.10.2021 17:43, Sam Protsenko wrote:
>>> Provide dt-schema documentation for Exynos850 SoC clock controller.
>>>
>>> Signed-off-by: Sam Protsenko <[e-mail]>
>>> Reviewed-by: Krzysztof Kozlowski <[e-mail]>
>>> Acked-by: Chanwoo Choi <[e-mail]>
[...]
>>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
>>> @@ -0,0 +1,185 @@
[...]
>>> +
>>> +title: Samsung Exynos850 SoC clock controller
>>> +
>>> +maintainers:
>>> +  - Sam Protsenko <[e-mail]>
>>> +  - Chanwoo Choi <[e-mail]>
>>> +  - Krzysztof Kozlowski <[e-mail]>
>>> +  - Sylwester Nawrocki <[e-mail]>
>>> +  - Tomasz Figa <[e-mail]>
>>> +
>>> +description: |
>>> +  Exynos850 clock controller is comprised of several CMU units, generating
>>> +  clocks for different domains. Those CMU units are modeled as separate device
>>> +  tree nodes, and might depend on each other. Root clocks in that clock tree are
>>> +  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
>>> +  clocks must be defined as fixed-rate clocks in dts.
>>> +
>>> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
>>> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
>>> +
>>> +  Each clock is assigned an identifier and client nodes can use this identifier
>>> +  to specify the clock which they consume. All clocks that available for usage
>>
>> s/All clocks that available/All clocks available ?
>> No need to resend, I can amend it when applying.
>>
> 
> Yeah, not a native speaker, I tend to do such mistakes sometimes :)
> Please fix when applying.
> 
> Btw, I can see that you already applied 3 out of 5 patches from this
> patch series here: [1]. Can you please also apply the rest, or is
> there any outstanding comments that I missed?

The patches look good to me, I just wanted to allow some for Rob to have
a look and provide an Ack.

Regards,

Sam Protsenko Oct. 12, 2021, 8:13 a.m. UTC | #4

Hi Rob,

On Mon, 11 Oct 2021 at 13:42, Sylwester Nawrocki <[e-mail]> wrote:
>
> On 11.10.2021 12:13, Sam Protsenko wrote:
> > On Sat, 9 Oct 2021 at 23:41, Sylwester Nawrocki <[e-mail]> wrote:
> >>
> >> On 08.10.2021 17:43, Sam Protsenko wrote:
> >>> Provide dt-schema documentation for Exynos850 SoC clock controller.
> >>>
> >>> Signed-off-by: Sam Protsenko <[e-mail]>
> >>> Reviewed-by: Krzysztof Kozlowski <[e-mail]>
> >>> Acked-by: Chanwoo Choi <[e-mail]>
> [...]
> >>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> >>> @@ -0,0 +1,185 @@
> [...]
> >>> +
> >>> +title: Samsung Exynos850 SoC clock controller
> >>> +
> >>> +maintainers:
> >>> +  - Sam Protsenko <[e-mail]>
> >>> +  - Chanwoo Choi <[e-mail]>
> >>> +  - Krzysztof Kozlowski <[e-mail]>
> >>> +  - Sylwester Nawrocki <[e-mail]>
> >>> +  - Tomasz Figa <[e-mail]>
> >>> +
> >>> +description: |
> >>> +  Exynos850 clock controller is comprised of several CMU units, generating
> >>> +  clocks for different domains. Those CMU units are modeled as separate device
> >>> +  tree nodes, and might depend on each other. Root clocks in that clock tree are
> >>> +  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
> >>> +  clocks must be defined as fixed-rate clocks in dts.
> >>> +
> >>> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
> >>> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
> >>> +
> >>> +  Each clock is assigned an identifier and client nodes can use this identifier
> >>> +  to specify the clock which they consume. All clocks that available for usage
> >>
> >> s/All clocks that available/All clocks available ?
> >> No need to resend, I can amend it when applying.
> >>
> >
> > Yeah, not a native speaker, I tend to do such mistakes sometimes :)
> > Please fix when applying.
> >
> > Btw, I can see that you already applied 3 out of 5 patches from this
> > patch series here: [1]. Can you please also apply the rest, or is
> > there any outstanding comments that I missed?
>
> The patches look good to me, I just wanted to allow some for Rob to have
> a look and provide an Ack.
>

Can you please review this one?

Thanks!

> Regards,
> --
> Sylwester Nawrocki
> Samsung R&D Institute Poland

Sylwester Nawrocki Oct. 15, 2021, 1:46 p.m. UTC | #5

On 12.10.2021 10:13, Sam Protsenko wrote:
> On Mon, 11 Oct 2021 at 13:42, Sylwester Nawrocki<[e-mail]>  wrote:
>> On 11.10.2021 12:13, Sam Protsenko wrote:
>>> On Sat, 9 Oct 2021 at 23:41, Sylwester Nawrocki<[e-mail]>  wrote:
>>>> On 08.10.2021 17:43, Sam Protsenko wrote:
>>>>> Provide dt-schema documentation for Exynos850 SoC clock controller.
>>>>>
>>>>> Signed-off-by: Sam Protsenko<[e-mail]>
>>>>> Reviewed-by: Krzysztof Kozlowski<[e-mail]>
>>>>> Acked-by: Chanwoo Choi<[e-mail]>
>> [...]
>>>>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
>>>>> @@ -0,0 +1,185 @@
>> [...]
>>>>> +
>>>>> +title: Samsung Exynos850 SoC clock controller
>>>>> +
>>>>> +maintainers:
>>>>> +  - Sam Protsenko<[e-mail]>
>>>>> +  - Chanwoo Choi<[e-mail]>
>>>>> +  - Krzysztof Kozlowski<[e-mail]>
>>>>> +  - Sylwester Nawrocki<[e-mail]>
>>>>> +  - Tomasz Figa<[e-mail]>
>>>>> +
>>>>> +description: |
>>>>> +  Exynos850 clock controller is comprised of several CMU units, generating
>>>>> +  clocks for different domains. Those CMU units are modeled as separate device
>>>>> +  tree nodes, and might depend on each other. Root clocks in that clock tree are
>>>>> +  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
>>>>> +  clocks must be defined as fixed-rate clocks in dts.
>>>>> +
>>>>> +  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
>>>>> +  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
>>>>> +
>>>>> +  Each clock is assigned an identifier and client nodes can use this identifier
>>>>> +  to specify the clock which they consume. All clocks that available for usage

>>>> s/All clocks that available/All clocks available ?
>>>> No need to resend, I can amend it when applying.
>>>>
>>> Yeah, not a native speaker, I tend to do such mistakes sometimes:)
>>> Please fix when applying.
>>>
>>> Btw, I can see that you already applied 3 out of 5 patches from this
>>> patch series here: [1]. Can you please also apply the rest, or is
>>> there any outstanding comments that I missed?
>> The patches look good to me, I just wanted to allow some for Rob to have
>> a look and provide an Ack.
>>
> Can you please review this one?

The binding is rather straightforward so I applied the patch now, thank you.

Patch

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
new file mode 100644
index 000000000000..79202e6e6402
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -0,0 +1,185 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos850 SoC clock controller
+
+maintainers:
+  - Sam Protsenko <[e-mail]>
+  - Chanwoo Choi <[e-mail]>
+  - Krzysztof Kozlowski <[e-mail]>
+  - Sylwester Nawrocki <[e-mail]>
+  - Tomasz Figa <[e-mail]>
+
+description: |
+  Exynos850 clock controller is comprised of several CMU units, generating
+  clocks for different domains. Those CMU units are modeled as separate device
+  tree nodes, and might depend on each other. Root clocks in that clock tree are
+  two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
+  clocks must be defined as fixed-rate clocks in dts.
+
+  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
+  dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP.
+
+  Each clock is assigned an identifier and client nodes can use this identifier
+  to specify the clock which they consume. All clocks that available for usage
+  in clock consumer nodes are defined as preprocessor macros in
+  'dt-bindings/clock/exynos850.h' header.
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos850-cmu-top
+      - samsung,exynos850-cmu-core
+      - samsung,exynos850-cmu-dpu
+      - samsung,exynos850-cmu-hsi
+      - samsung,exynos850-cmu-peri
+
+  clocks:
+    minItems: 1
+    maxItems: 5
+
+  clock-names:
+    minItems: 1
+    maxItems: 5
+
+  "#clock-cells":
+    const: 1
+
+  reg:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-top
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+
+        clock-names:
+          items:
+            - const: oscclk
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-core
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_CORE bus clock (from CMU_TOP)
+            - description: CCI clock (from CMU_TOP)
+            - description: eMMC clock (from CMU_TOP)
+            - description: SSS clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_core_bus
+            - const: dout_core_cci
+            - const: dout_core_mmc_embd
+            - const: dout_core_sss
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-dpu
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: DPU clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_dpu
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-hsi
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: External RTC clock (32768 Hz)
+            - description: CMU_HSI bus clock (from CMU_TOP)
+            - description: SD card clock (from CMU_TOP)
+            - description: "USB 2.0 DRD clock (from CMU_TOP)"
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: rtcclk
+            - const: dout_hsi_bus
+            - const: dout_hsi_mmc_card
+            - const: dout_hsi_usb20drd
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos850-cmu-peri
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_PERI bus clock (from CMU_TOP)
+            - description: UART clock (from CMU_TOP)
+            - description: Parent clock for HSI2C and SPI (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_peri_bus
+            - const: dout_peri_uart
+            - const: dout_peri_ip
+
+required:
+  - compatible
+  - "#clock-cells"
+  - clocks
+  - clock-names
+  - reg
+
+additionalProperties: false
+
+examples:
+  # Clock controller node for CMU_PERI
+  - |
+    #include <dt-bindings/clock/exynos850.h>
+
+    cmu_peri: clock-controller@10030000 {
+        compatible = "samsung,exynos850-cmu-peri";
+        reg = <0x10030000 0x8000>;
+        #clock-cells = <1>;
+
+        clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>,
+                 <&cmu_top CLK_DOUT_PERI_UART>,
+                 <&cmu_top CLK_DOUT_PERI_IP>;
+        clock-names = "oscclk", "dout_peri_bus",
+                      "dout_peri_uart", "dout_peri_ip";
+    };
+
+...