From patchwork Mon Oct 11 16:57:00 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hector Martin X-Patchwork-Id: 12550615 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 333B7C433FE for ; Mon, 11 Oct 2021 17:00:41 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 007CA60FD7 for ; Mon, 11 Oct 2021 17:00:40 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 007CA60FD7 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=marcan.st Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=oHmCrXNKIQTuRnRFysVNG3IAZBydm+SOSN2wgSDEwYI=; b=nK4PumWqSKBh17 TfiSdkovjnEY6/o3HbzOHdbvwhCNZnKfOoF4WwXxBzgmt/c71LwSVoy9uFnBQRNIZYIBRAmr/ay/g 5KX6uiZKnaXfcIhpIo7rVf0Lxp1dL1wWzlR0PLUDRRB9JH7YR0lRWmgmeE6mmhABbK5ZfrxaoeoJZ hpubenhOqQPUtySIUbfWs21nRCjfTWBD4vHmWa9gulXDrNBak00fjB67jgbIFRZ/pw+o15Ab0lVb8 5bCKPDBnHsmfQ2vSNB++4SHcQfBAhH1o/Z2/RM18EdMKTGMje5UY870u92/tj+gCkainlQB2RhQi9 ViMzMFbDa0V50JsjewVQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZych-00A8KK-VF; Mon, 11 Oct 2021 16:58:00 +0000 Received: from marcansoft.com ([2a01:298:fe:f::2] helo=mail.marcansoft.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mZycQ-00A8Fb-3j for linux-arm-kernel@lists.infradead.org; Mon, 11 Oct 2021 16:57:43 +0000 Received: from [127.0.0.1] (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: hector@marcansoft.com) by mail.marcansoft.com (Postfix) with ESMTPSA id 510E642446; Mon, 11 Oct 2021 16:57:35 +0000 (UTC) From: Hector Martin To: linux-arm-kernel@lists.infradead.org Cc: Hector Martin , Alyssa Rosenzweig , Sven Peter , Marc Zyngier , Mark Kettenis , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Viresh Kumar , Nishanth Menon , Catalin Marinas , "Rafael J. Wysocki" , Kevin Hilman , Ulf Hansson , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/9] dt-bindings: memory-controller: Add apple, mcc binding Date: Tue, 12 Oct 2021 01:57:00 +0900 Message-Id: <20211011165707.138157-3-marcan@marcan.st> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211011165707.138157-1-marcan@marcan.st> References: <20211011165707.138157-1-marcan@marcan.st> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211011_095742_327091_64806752 X-CRM114-Status: GOOD ( 16.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This device represents the memory controller in Apple SoCs, and is chiefly in charge of adjusting performance characteristics according to system demand. Signed-off-by: Hector Martin --- .../memory-controllers/apple,mcc.yaml | 80 +++++++++++++++++++ .../opp/apple,mcc-operating-points.yaml | 62 ++++++++++++++ 2 files changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml create mode 100644 Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml b/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml new file mode 100644 index 000000000000..0774f10e65ed --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/apple,mcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC MCC memory controller performance controls + +maintainers: + - Hector Martin + +description: | + Apple SoCs contain a multichannel memory controller that can have its + configuration changed to adjust to changing performance requirements from + the rest of the SoC. This node represents the controller and provides a + power domain provider that downstream devices can use to adjust the memory + controller performance level. + +properties: + compatible: + items: + - enum: + - apple,t8103-mcc + - const: apple,mcc + + reg: + maxItems: 1 + + "#power-domain-cells": + const: 0 + + operating-points-v2: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A reference to the OPP table describing the memory controller performance + levels. Each OPP node should contain an `apple,memory-perf-config` + property that contains the configuration values for that performance + level. + + apple,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + The number of memory channels in use. + +required: + - compatible + - reg + - "#power-domain-cells" + - operating-points-v2 + - apple,num-channels + +additionalProperties: false + +examples: + # See clock/apple,cluster-clock.yaml for an example of downstream usage. + - | + mcc_opp: opp-table-2 { + compatible = "operating-points-v2"; + + mcc_lowperf: opp0 { + opp-level = <0>; + apple,memory-perf-config = <0x813057f 0x1800180>; + }; + mcc_highperf: opp1 { + opp-level = <1>; + apple,memory-perf-config = <0x133 0x55555340>; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + + mcc: memory-controller@200200000 { + compatible = "apple,t8103-mcc", "apple,mcc"; + #power-domain-cells = <0>; + reg = <0x2 0x200000 0x0 0x200000>; + operating-points-v2 = <&mcc_opp>; + apple,num-channels = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml b/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml new file mode 100644 index 000000000000..babf27841bb7 --- /dev/null +++ b/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/opp/apple,mcc-operating-points.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SoC memory controller OPP bindings + +maintainers: + - Hector Martin + +description: | + Apple SoCs can have their memory controller performance adjusted depending on + system requirements. These performance states are represented by specific + memory controller register values. The apple-mcc driver uses these values + to change the MCC performance. + +allOf: + - $ref: opp-v2-base.yaml# + +properties: + compatible: + const: apple,mcc-operating-points + +required: + - compatible + +patternProperties: + "opp[0-9]+": + type: object + + properties: + opp-level: true + apple,memory-perf-config: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + A pair of register values used to configure this performance state. + minItems: 2 + maxItems: 2 + + required: + - opp-level + - apple,memory-perf-config + + unevaluatedProperties: false + +additionalProperties: false + +examples: + - | + mcc_opp: opp-table-2 { + compatible = "operating-points-v2"; + + mcc_lowperf: opp0 { + opp-level = <0>; + apple,memory-perf-config = <0x813057f 0x1800180>; + }; + mcc_highperf: opp1 { + opp-level = <1>; + apple,memory-perf-config = <0x133 0x55555340>; + }; + };