| Message ID | 20211014223125.2605031-4-suzuki.poulose@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Self-hosted trace related errata workarounds | expand |
On 10/15/21 4:01 AM, Suzuki K Poulose wrote: > Arm Neoverse-N2 (#2067961) and Cortex-A710 (#2054223) suffers > from errata, where a TSB (trace synchronization barrier) > fails to flush the trace data completely, when executed from > a trace prohibited region. In Linux we always execute it > after we have moved the PE to trace prohibited region. So, > we can apply the workaround every time a TSB is executed. > > The work around is to issue two TSB consecutively. > > NOTE: This errata is defined as LOCAL_CPU_ERRATUM, implying > that a late CPU could be blocked from booting if it is the > first CPU that requires the workaround. This is because we > do not allow setting a cpu_hwcaps after the SMP boot. The > other alternative is to use "this_cpu_has_cap()" instead > of the faster system wide check, which may be a bit of an > overhead, given we may have to do this in nvhe KVM host > before a guest entry. > > Cc: Will Deacon <will@kernel.org> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Mathieu Poirier <mathieu.poirier@linaro.org> > Cc: Mike Leach <mike.leach@linaro.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Anshuman Khandual <anshuman.khandual@arm.com> > Cc: Marc Zyngier <maz@kernel.org> > Acked-by: Catalin Marinas <catalin.marinas@arm.com> > Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com> > --- > Changes since v3: > - Merge the Kconfig changes back. > --- > Documentation/arm64/silicon-errata.rst | 4 ++++ > arch/arm64/Kconfig | 33 ++++++++++++++++++++++++++ > arch/arm64/include/asm/barrier.h | 16 ++++++++++++- > arch/arm64/kernel/cpu_errata.c | 19 +++++++++++++++ > arch/arm64/tools/cpucaps | 1 + > 5 files changed, 72 insertions(+), 1 deletion(-) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index 2f99229d993c..569a92411dcd 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -94,6 +94,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N1 | #1349291 | N/A | > @@ -102,6 +104,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | MMU-500 | #841119,826419 | N/A | > +----------------+-----------------+-----------------+-----------------------------+ > +----------------+-----------------+-----------------+-----------------------------+ > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b452181d3638..39b78460b9d0 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -707,6 +707,39 @@ config ARM64_ERRATUM_2139208 > > If unsure, say Y. > > +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE > + bool > + > +config ARM64_ERRATUM_2054223 > + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" > + default y > + select ARM64_WORKAROUND_TSB_FLUSH_FAILURE > + help > + Enable workaround for ARM Cortex-A710 erratum 2054223 > + > + Affected cores may fail to flush the trace data on a TSB instruction, when > + the PE is in trace prohibited state. This will cause losing a few bytes > + of the trace cached. > + > + Workaround is to issue two TSB consecutively on affected cores. > + > + If unsure, say Y. > + > +config ARM64_ERRATUM_2067961 > + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" > + default y > + select ARM64_WORKAROUND_TSB_FLUSH_FAILURE > + help > + Enable workaround for ARM Neoverse-N2 erratum 2067961 > + > + Affected cores may fail to flush the trace data on a TSB instruction, when > + the PE is in trace prohibited state. This will cause losing a few bytes > + of the trace cached. > + > + Workaround is to issue two TSB consecutively on affected cores. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h > index 451e11e5fd23..1c5a00598458 100644 > --- a/arch/arm64/include/asm/barrier.h > +++ b/arch/arm64/include/asm/barrier.h > @@ -23,7 +23,7 @@ > #define dsb(opt) asm volatile("dsb " #opt : : : "memory") > > #define psb_csync() asm volatile("hint #17" : : : "memory") > -#define tsb_csync() asm volatile("hint #18" : : : "memory") > +#define __tsb_csync() asm volatile("hint #18" : : : "memory") > #define csdb() asm volatile("hint #20" : : : "memory") > > #ifdef CONFIG_ARM64_PSEUDO_NMI > @@ -46,6 +46,20 @@ > #define dma_rmb() dmb(oshld) > #define dma_wmb() dmb(oshst) > > + > +#define tsb_csync() \ > + do { \ > + /* \ > + * CPUs affected by Arm Erratum 2054223 or 2067961 needs \ > + * another TSB to ensure the trace is flushed. The barriers \ > + * don't have to be strictly back to back, as long as the \ > + * CPU is in trace prohibited state. \ > + */ \ > + if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE)) \ > + __tsb_csync(); \ > + __tsb_csync(); \ > + } while (0) > + > /* > * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz > * and 0 otherwise. > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index ccd757373f36..bdbeac75ead6 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ > > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE > +static const struct midr_range tsb_flush_fail_cpus[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2067961 > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2054223 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > +#endif > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > + { > + .desc = "ARM erratum 2067961 or 2054223", > + .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, > + ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 1ccb92165bd8..2102e15af43d 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -54,6 +54,7 @@ WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > +WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_CAVIUM_23154 > WORKAROUND_CAVIUM_27456 > WORKAROUND_CAVIUM_30115 >
On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index ccd757373f36..bdbeac75ead6 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { > }; > #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ > > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE > +static const struct midr_range tsb_flush_fail_cpus[] = { > +#ifdef CONFIG_ARM64_ERRATUM_2067961 > + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_2054223 > + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), > +#endif > + {}, > +}; > +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ > + > const struct arm64_cpu_capabilities arm64_errata[] = { > #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE > { > @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), > }, > +#endif > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE You still haven't fixed this typo... Seriously, I get compile warnings from this -- are you not seeing them? Will
On 19/10/2021 12:02, Will Deacon wrote: > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >> index ccd757373f36..bdbeac75ead6 100644 >> --- a/arch/arm64/kernel/cpu_errata.c >> +++ b/arch/arm64/kernel/cpu_errata.c >> @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { >> }; >> #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ >> >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE >> +static const struct midr_range tsb_flush_fail_cpus[] = { >> +#ifdef CONFIG_ARM64_ERRATUM_2067961 >> + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), >> +#endif >> +#ifdef CONFIG_ARM64_ERRATUM_2054223 >> + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), >> +#endif >> + {}, >> +}; >> +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ >> + >> const struct arm64_cpu_capabilities arm64_errata[] = { >> #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE >> { >> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >> }, >> +#endif >> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > You still haven't fixed this typo... > Sorry about that. I thought it was about selecting the Kconfig entries, which was fixed. I will fix this. > Seriously, I get compile warnings from this -- are you not seeing them? No, I don't get any warnings. Is there something that I am missing ? --8>-- suzuki@ewhatever:coresight$ grep "WERROR\|TSB" .config CONFIG_WERROR=y CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ grep TSB arch/arm64/kernel/cpu_errata.c #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE #endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ #ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, suzuki@ewhatever:coresight$ touch arch/arm64/kernel/cpu_errata.c suzuki@ewhatever:coresight$ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o AR arch/arm64/kernel/built-in.a AR arch/arm64/built-in.a GEN .version CHK include/generated/compile.h UPD include/generated/compile.h CC init/version.o AR init/built-in.a LD vmlinux.o MODPOST vmlinux.symvers MODINFO modules.builtin.modinfo GEN modules.builtin LD .tmp_vmlinux.kallsyms1 KSYMS .tmp_vmlinux.kallsyms1.S AS .tmp_vmlinux.kallsyms1.S LD .tmp_vmlinux.kallsyms2 KSYMS .tmp_vmlinux.kallsyms2.S AS .tmp_vmlinux.kallsyms2.S LD vmlinux SORTTAB vmlinux SYSMAP System.map MODPOST modules-only.symvers OBJCOPY arch/arm64/boot/Image GEN Module.symvers GZIP arch/arm64/boot/Image.gz Suzuki > > Will >
On Tue, Oct 19, 2021 at 12:36:48PM +0100, Suzuki K Poulose wrote: > On 19/10/2021 12:02, Will Deacon wrote: > > On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: > > > @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > > > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, > > > CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), > > > }, > > > +#endif > > > +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE > > > > You still haven't fixed this typo... > > > > Sorry about that. I thought it was about selecting the > Kconfig entries, which was fixed. I will fix this. Sorry, I thought it was such a howler that it would've jumped out ;) That's what made me think we should make sure the series compiles without the coresight changes, so we can catch these problems early. > > Seriously, I get compile warnings from this -- are you not seeing them? > > No, I don't get any warnings. Is there something that I am missing ? Interesting. I see the warning below in my bisection testing, since the typo means that the midr lookup table isn't used. Maybe you're only compiling the end result? Will --->8 +arch/arm64/kernel/cpu_errata.c:356:32: warning: ‘tsb_flush_fail_cpus’ defined but not used [-Wunused-const-variable=] + 356 | static const struct midr_range tsb_flush_fail_cpus[] = { + | ^~~~~~~~~~~~~~~~~~~
On 19/10/2021 12:42, Will Deacon wrote: > On Tue, Oct 19, 2021 at 12:36:48PM +0100, Suzuki K Poulose wrote: >> On 19/10/2021 12:02, Will Deacon wrote: >>> On Thu, Oct 14, 2021 at 11:31:13PM +0100, Suzuki K Poulose wrote: >>>> @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>>> .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, >>>> CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), >>>> }, >>>> +#endif >>>> +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE >>> >>> You still haven't fixed this typo... >>> >> >> Sorry about that. I thought it was about selecting the >> Kconfig entries, which was fixed. I will fix this. > > Sorry, I thought it was such a howler that it would've jumped out ;) > That's what made me think we should make sure the series compiles without > the coresight changes, so we can catch these problems early. > >>> Seriously, I get compile warnings from this -- are you not seeing them? >> >> No, I don't get any warnings. Is there something that I am missing ? > > Interesting. I see the warning below in my bisection testing, since the typo > means that the midr lookup table isn't used. Maybe you're only compiling the > end result? No, I was compiling this at the commit. Also, please note that the TSB flush failure config is enabled with the patch, unlike the TRBE errata ones. My GCC is : gcc version 9.3.1 20200408 (Red Hat 9.3.1-2) (GCC) $ grep TSB arch/arm64/Kconfig arch/arm64/kernel/cpu_errata.c .config arch/arm64/Kconfig:config ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/Kconfig: bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" arch/arm64/Kconfig: select ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/Kconfig: Affected cores may fail to flush the trace data on a TSB instruction, when arch/arm64/Kconfig: Workaround is to issue two TSB consecutively on affected cores. arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE arch/arm64/kernel/cpu_errata.c:#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ arch/arm64/kernel/cpu_errata.c:#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE arch/arm64/kernel/cpu_errata.c: .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, .config:CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y suzuki@ewhatever:coresight$ git log --oneline -1 89e0c94bd734 (HEAD) arm64: errata: Add workaround for TSB flush failures > > Will > > --->8 > > +arch/arm64/kernel/cpu_errata.c:356:32: warning: ‘tsb_flush_fail_cpus’ defined but not used [-Wunused-const-variable=] > + 356 | static const struct midr_range tsb_flush_fail_cpus[] = { > + | ^~~~~~~~~~~~~~~~~~~ > That looks a valid warning. Hmm, strange. It does complain for an unused function though. $ make -j16 CALL scripts/atomic/check-atomics.sh CALL scripts/checksyscalls.sh CHK include/generated/compile.h CC arch/arm64/kernel/cpu_errata.o arch/arm64/kernel/cpu_errata.c:90:13: error: ‘here_is_an_unused_function’ defined but not used [-Werror=unused-function] static void here_is_an_unused_function(void) ^~~~~~~~~~~~~~~~~~~~~~~~~~ cc1: all warnings being treated as errors make[2]: *** [scripts/Makefile.build:277: arch/arm64/kernel/cpu_errata.o] Error 1 make[1]: *** [scripts/Makefile.build:540: arch/arm64/kernel] Error 2 make: *** [Makefile:1874: arch/arm64] Error 2 make: *** Waiting for unfinished jobs.... --8>-- diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index aaa66c9eee24..57c83e84b274 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -87,12 +87,20 @@ has_mismatched_cache_type(const struct arm64_cpu_capabilities *entry, return (ctr_real != sys) && (ctr_raw != sys); } +static void here_is_an_unused_function(void) +{ + pr_crit("I am unused\n"); +} + static void cpu_enable_trap_ctr_access(const struct arm64_cpu_capabilities *cap) { u64 mask = arm64_ftr_reg_ctrel0.strict_mask; bool enable_uct_trap = false; +#ifdef CONFIG_UNUSED_FUNCTION + here_is_an_unused_function(); +#endif Cheers Suzuki
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 2f99229d993c..569a92411dcd 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -94,6 +94,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | @@ -102,6 +104,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index b452181d3638..39b78460b9d0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -707,6 +707,39 @@ config ARM64_ERRATUM_2139208 If unsure, say Y. +config ARM64_WORKAROUND_TSB_FLUSH_FAILURE + bool + +config ARM64_ERRATUM_2054223 + bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace" + default y + select ARM64_WORKAROUND_TSB_FLUSH_FAILURE + help + Enable workaround for ARM Cortex-A710 erratum 2054223 + + Affected cores may fail to flush the trace data on a TSB instruction, when + the PE is in trace prohibited state. This will cause losing a few bytes + of the trace cached. + + Workaround is to issue two TSB consecutively on affected cores. + + If unsure, say Y. + +config ARM64_ERRATUM_2067961 + bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace" + default y + select ARM64_WORKAROUND_TSB_FLUSH_FAILURE + help + Enable workaround for ARM Neoverse-N2 erratum 2067961 + + Affected cores may fail to flush the trace data on a TSB instruction, when + the PE is in trace prohibited state. This will cause losing a few bytes + of the trace cached. + + Workaround is to issue two TSB consecutively on affected cores. + + If unsure, say Y. + config CAVIUM_ERRATUM_22375 bool "Cavium erratum 22375, 24313" default y diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index 451e11e5fd23..1c5a00598458 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -23,7 +23,7 @@ #define dsb(opt) asm volatile("dsb " #opt : : : "memory") #define psb_csync() asm volatile("hint #17" : : : "memory") -#define tsb_csync() asm volatile("hint #18" : : : "memory") +#define __tsb_csync() asm volatile("hint #18" : : : "memory") #define csdb() asm volatile("hint #20" : : : "memory") #ifdef CONFIG_ARM64_PSEUDO_NMI @@ -46,6 +46,20 @@ #define dma_rmb() dmb(oshld) #define dma_wmb() dmb(oshst) + +#define tsb_csync() \ + do { \ + /* \ + * CPUs affected by Arm Erratum 2054223 or 2067961 needs \ + * another TSB to ensure the trace is flushed. The barriers \ + * don't have to be strictly back to back, as long as the \ + * CPU is in trace prohibited state. \ + */ \ + if (cpus_have_final_cap(ARM64_WORKAROUND_TSB_FLUSH_FAILURE)) \ + __tsb_csync(); \ + __tsb_csync(); \ + } while (0) + /* * Generate a mask for array_index__nospec() that is ~0UL when 0 <= idx < sz * and 0 otherwise. diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index ccd757373f36..bdbeac75ead6 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -352,6 +352,18 @@ static const struct midr_range trbe_overwrite_fill_mode_cpus[] = { }; #endif /* CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE */ +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE +static const struct midr_range tsb_flush_fail_cpus[] = { +#ifdef CONFIG_ARM64_ERRATUM_2067961 + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), +#endif +#ifdef CONFIG_ARM64_ERRATUM_2054223 + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), +#endif + {}, +}; +#endif /* CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE */ + const struct arm64_cpu_capabilities arm64_errata[] = { #ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE { @@ -558,6 +570,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, CAP_MIDR_RANGE_LIST(trbe_overwrite_fill_mode_cpus), }, +#endif +#ifdef CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILRE + { + .desc = "ARM erratum 2067961 or 2054223", + .capability = ARM64_WORKAROUND_TSB_FLUSH_FAILURE, + ERRATA_MIDR_RANGE_LIST(tsb_flush_fail_cpus), + }, #endif { } diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 1ccb92165bd8..2102e15af43d 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -54,6 +54,7 @@ WORKAROUND_1463225 WORKAROUND_1508412 WORKAROUND_1542419 WORKAROUND_TRBE_OVERWRITE_FILL_MODE +WORKAROUND_TSB_FLUSH_FAILURE WORKAROUND_CAVIUM_23154 WORKAROUND_CAVIUM_27456 WORKAROUND_CAVIUM_30115