Message ID | 20211020094656.3343242-4-claudiu.beznea@microchip.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
Return-Path: <SRS0=+LcQ=PI=lists.infradead.org=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@kernel.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 49C38C433EF for <linux-arm-kernel@archiver.kernel.org>; Wed, 20 Oct 2021 09:49:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1AF2A6135E for <linux-arm-kernel@archiver.kernel.org>; Wed, 20 Oct 2021 09:49:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 1AF2A6135E Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=microchip.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gGYGoblZryXsHP0q4AY+aQI8w1fexqumRYPD9AIxtAs=; b=P/TNthudOxXdPd HrRnJKCfYvrPhdnX7DspoDRYu+iOEXzhQwXUs0YnFveK+er25vVMaIwIbUbC1pLTtO6akp91LabIe Gtfp4bVeFZGscO+rRlnie0sNhqUPDZ44VfAvVYTU4oNPPDxllm+U8+WWvODcw28cG2AMVARu2BuWL N2zcclw0ickwlWgvMBL4vohs2HpxYuIE6m2NoVR9XASrbYoLhTuTlGzOHV+TM/9YofN6QFMhxbMQz jsAb11OfqMwPgtKO53JMXxQSw99BtDeeUx0qkWUHlhI4g6igmv74Lcc+IMV+He3lPBrvkKKMAPB22 o+wn0LXC+tyw7zMiOjsQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1md8CM-0042pk-5S; Wed, 20 Oct 2021 09:47:50 +0000 Received: from esa.microchip.iphmx.com ([68.232.154.123]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1md8Bo-0042gr-8F for linux-arm-kernel@lists.infradead.org; Wed, 20 Oct 2021 09:47:17 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1634723236; x=1666259236; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=URipOdsLH8qC+kXFhsmFA9PY9uWuO/jRnDNcvGWY+Ng=; b=RmEoepO3Zxb7440Z+I2NMzcyYJ6T/yol5TEUVADkGsWQFuz5faH82LGf Uk4qqN/f5vWL6JcZNarEHY7hkZ8V0yotmfI2oMflXz2L6MHGJmR/t+edP cKPTv6CcNTQRiyjm2bXirZYQRVXVtBeiS4wy0wFXFLy2z1opyXGAQRzHj a6lTeDorV97UcfmMGmAdrlJqFQIeSEDGSQBRkmAuOmra6mYh9UFGBcsvw qn6mp8JfgJy5rsgPqpYHpSHjYVygmVxnymgk1LGYZeUduCGkT8DmrlHMU /FPQxRbNrs0x7pEVzgFTJDfENpEmSVK8dMK0BjtYZ9HEV9pkbDnb8b7RR w==; IronPort-SDR: 0Ivpew15024BrrpqJAYuw8rPcBRubCaQkm5Sw4bOf4H23UDixpvPun/51Up5kMDoH1DNt5Nt3Q wOKYFvbxedr25kdOL9V6bY2j+C5dRJiq4Aw7rzRaEKF7k2M+0D/fSaeMlaHTgZcLHqvCK5I/QC X5v6m4pgt3eF3v22b+NBcGpv6IkKFEx2osFh2vRl+HUlBN26x0DQfWSO5Dm/KaGSWrRZ7f/D6t 2L5GuNNhRGKRTDzweVqV03+5NQBWnGi0FEdB3QAYO/vibL4DgvOIeF2b5rYz4XJMCoeaYd8/3W 0TtNyE4I9978ULTKEU7Aj5ap X-IronPort-AV: E=Sophos;i="5.87,166,1631602800"; d="scan'208";a="133739628" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 20 Oct 2021 02:47:15 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Wed, 20 Oct 2021 02:47:14 -0700 Received: from rob-dk-mpu01.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Wed, 20 Oct 2021 02:47:12 -0700 From: Claudiu Beznea <claudiu.beznea@microchip.com> To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>, <ludovic.desroches@microchip.com>, <robh+dt@kernel.org> CC: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Claudiu Beznea <claudiu.beznea@microchip.com> Subject: [PATCH 3/3] ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce Date: Wed, 20 Oct 2021 12:46:56 +0300 Message-ID: <20211020094656.3343242-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com> References: <20211020094656.3343242-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211020_024716_381326_6292B39D X-CRM114-Status: UNSURE ( 9.80 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-arm-kernel.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> List-Post: <mailto:linux-arm-kernel@lists.infradead.org> List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org |
Series |
ARM: dts: at91: enable leftover IPs
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diff --git a/arch/arm/boot/dts/at91-sama7g5ek.dts b/arch/arm/boot/dts/at91-sama7g5ek.dts index 0f53b2db28a2..0e1975c6812e 100644 --- a/arch/arm/boot/dts/at91-sama7g5ek.dts +++ b/arch/arm/boot/dts/at91-sama7g5ek.dts @@ -687,6 +687,18 @@ &spdiftx { status = "okay"; }; +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + &trng { status = "okay"; };
Use blocks 0 and 1 of TCB0 for clocksource and clockevent functionality. PIT64B is already enabled on SAMA7G5 targets for this but TCB0 will be used as a fallback only in case PIT64B will fail to probe. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> --- arch/arm/boot/dts/at91-sama7g5ek.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+)