diff mbox series

[RFC,V2,1/5] arm64: dts: imx8mm: Add CSI nodes

Message ID 20211023203457.1217821-2-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: imx8mm: Enable CSI and OV5640 Camera | expand

Commit Message

Adam Ford Oct. 23, 2021, 8:34 p.m. UTC 
There is a csi bridge and csis interface that tie together
to allow csi2 capture.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++
 1 file changed, 55 insertions(+)

Comments

Laurent Pinchart Oct. 28, 2021, 2:03 a.m. UTC | #1 
Hi Adam,

Thank you for the patch.

On Sat, Oct 23, 2021 at 03:34:52PM -0500, Adam Ford wrote:
> There is a csi bridge and csis interface that tie together
> to allow csi2 capture.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mm.dtsi | 55 +++++++++++++++++++++++
>  1 file changed, 55 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c2f3f118f82e..920f9041ef50 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -1068,6 +1068,22 @@ aips4: bus@32c00000 {
>  			#size-cells = <1>;
>  			ranges = <0x32c00000 0x32c00000 0x400000>;
>  
> +			csi: csi@32e20000 {
> +				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
> +				reg = <0x32e20000 0x1000>;
> +				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
> +				clock-names = "mclk";
> +				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
> +				status = "disabled";
> +
> +				port {
> +					csi_in: endpoint {
> +						remote-endpoint = <&imx8mm_mipi_csi_out>;
> +					};
> +				};
> +			};
> +
>  			disp_blk_ctrl: blk-ctrl@32e28000 {
>  				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
>  				reg = <0x32e28000 0x100>;
> @@ -1095,6 +1111,45 @@ disp_blk_ctrl: blk-ctrl@32e28000 {
>  				#power-domain-cells = <1>;
>  			};
>  
> +			mipi_csi2: mipi-csi@32e30000 {

I'd rename the label to mipi_csi to match the name in the reference
manual.

> +				compatible = "fsl,imx8mm-mipi-csi2";
> +				reg = <0x32e30000 0x1000>;
> +				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
> +						  <&clk IMX8MM_CLK_CSI1_PHY_REF>;
> +				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
> +							  <&clk IMX8MM_SYS_PLL2_1000M>;
> +				clock-frequency = <333000000>;
> +				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
> +					 <&clk IMX8MM_CLK_CSI1_ROOT>,
> +					 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
> +					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
> +				clock-names = "pclk", "wrap", "phy", "axi";
> +				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
> +				status = "disabled";
> +
> +				ports {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +
> +					port@0 {
> +						reg = <0>;
> +
> +						imx8mm_mipi_csi_in: endpoint {
> +						};

Empty ports are fine as they model the hardware, even when not
connected, but an endpoint models a connection, so it needs a remote
endpoint. You can drop the endpoint here, board DT files will create one
with

&mipi_csi {
	ports {
		port@0 {
			board_endpoint: endpoint {
				...
			};
		};
	};
};

> +					};
> +
> +					port@1 {
> +						reg = <1>;
> +
> +						imx8mm_mipi_csi_out: endpoint {
> +							remote-endpoint = <&csi_in>;
> +						};
> +					};
> +				};
> +			};
> +
> +

A single blank line is enough.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>  			usbotg1: usb@32e40000 {
>  				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
>  				reg = <0x32e40000 0x200>;
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index c2f3f118f82e..920f9041ef50 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1068,6 +1068,22 @@  aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges = <0x32c00000 0x32c00000 0x400000>;
 
+			csi: csi@32e20000 {
+				compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
+				reg = <0x32e20000 0x1000>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
+				clock-names = "mclk";
+				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
+				status = "disabled";
+
+				port {
+					csi_in: endpoint {
+						remote-endpoint = <&imx8mm_mipi_csi_out>;
+					};
+				};
+			};
+
 			disp_blk_ctrl: blk-ctrl@32e28000 {
 				compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
 				reg = <0x32e28000 0x100>;
@@ -1095,6 +1111,45 @@  disp_blk_ctrl: blk-ctrl@32e28000 {
 				#power-domain-cells = <1>;
 			};
 
+			mipi_csi2: mipi-csi@32e30000 {
+				compatible = "fsl,imx8mm-mipi-csi2";
+				reg = <0x32e30000 0x1000>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+				assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
+						  <&clk IMX8MM_CLK_CSI1_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
+							  <&clk IMX8MM_SYS_PLL2_1000M>;
+				clock-frequency = <333000000>;
+				clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_ROOT>,
+					 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
+					 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
+				clock-names = "pclk", "wrap", "phy", "axi";
+				power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
+				status = "disabled";
+
+				ports {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					port@0 {
+						reg = <0>;
+
+						imx8mm_mipi_csi_in: endpoint {
+						};
+					};
+
+					port@1 {
+						reg = <1>;
+
+						imx8mm_mipi_csi_out: endpoint {
+							remote-endpoint = <&csi_in>;
+						};
+					};
+				};
+			};
+
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;