@@ -435,6 +435,38 @@ static struct feature_config_ctrl ftr_ctrl_mte = {
.cfg_val = HCR_TID5,
};
+/* For ID_AA64DFR0_EL1 */
+static struct feature_config_ctrl ftr_ctrl_pmuv3 = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_PMUVER_SHIFT,
+ .ftr_min = ID_AA64DFR0_PMUVER_8_0,
+ .ftr_signed = FTR_UNSIGNED,
+ .cfg_reg = VCPU_MDCR_EL2,
+ .cfg_mask = MDCR_EL2_TPM,
+ .cfg_val = MDCR_EL2_TPM,
+};
+
+static struct feature_config_ctrl ftr_ctrl_pms = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_PMSVER_SHIFT,
+ .ftr_min = ID_AA64DFR0_PMSVER_8_2,
+ .ftr_signed = FTR_UNSIGNED,
+ .cfg_reg = VCPU_MDCR_EL2,
+ .cfg_mask = (MDCR_EL2_TPMS |
+ (MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT)),
+ .cfg_val = MDCR_EL2_TPMS,
+};
+
+static struct feature_config_ctrl ftr_ctrl_tracefilt = {
+ .ftr_reg = SYS_ID_AA64DFR0_EL1,
+ .ftr_shift = ID_AA64DFR0_TRACE_FILT_SHIFT,
+ .ftr_min = 1,
+ .ftr_signed = FTR_UNSIGNED,
+ .cfg_reg = VCPU_MDCR_EL2,
+ .cfg_mask = MDCR_EL2_TTRF,
+ .cfg_val = MDCR_EL2_TTRF,
+};
+
struct id_reg_info {
u32 sys_reg; /* Register ID */
u64 sys_val; /* Sanitized system value */
@@ -928,6 +960,12 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
.init = init_id_aa64dfr0_el1_info,
.validate = validate_id_aa64dfr0_el1,
.get_reset_val = get_reset_id_aa64dfr0_el1,
+ .trap_features = &(const struct feature_config_ctrl *[]) {
+ &ftr_ctrl_pmuv3,
+ &ftr_ctrl_pms,
+ &ftr_ctrl_tracefilt,
+ NULL,
+ },
};
static struct id_reg_info id_dfr0_el1_info = {
Add feature_config_ctrl for PMUv3, PMS and TraceFilt, which are indicated in ID_AA64DFR0_EL1, to program configuration registers to trap guest's using those features when they are not exposed to the guest. Signed-off-by: Reiji Watanabe <reijiw@google.com> --- arch/arm64/kvm/sys_regs.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)