From patchwork Thu Nov 4 10:59:14 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xuesong Chen X-Patchwork-Id: 12602843 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12331C433EF for ; Thu, 4 Nov 2021 11:01:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D3CCD61108 for ; Thu, 4 Nov 2021 11:01:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org D3CCD61108 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HWj+/I+7a4fzZEjc4bgAX9k8XEyB6pwxrlmfQD7se2g=; b=bd+PR+sbh9r5BV gcylojg6pxDhYRNOwweMhPS5J8/3V1XJivZl/fiXCaewLHapqf/nkqC9oaAu12YhYzSGq2JvZ1MBI 37y6MTMXrWj6/hE7cQktCyMQt9MgXrq3abDlUU335KCNWFM+zelUTFWYmZ7SwguHC4CVvS3iS45x8 u7U5HEFjj78ZCGzPVPjzINkln/7c3ubyhwpF+M6Y2ACn49yJF/hIODY0XVYauUn9QJuPiYFyC7Btd 0LIH4tD+9dyDwktHQmiDr/lGadQcOgTLTxgTKsyes5SQS9tJa82q7ziQGqO2CeqwX82CuoUtxpU8R 05dGUVDr1I/LXVg9s6zQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1miaT6-008d00-KM; Thu, 04 Nov 2021 10:59:40 +0000 Received: from out4436.biz.mail.alibaba.com ([47.88.44.36]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1miaT2-008cyu-Dk for linux-arm-kernel@lists.infradead.org; Thu, 04 Nov 2021 10:59:38 +0000 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R101e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=e01e04394; MF=xuesong.chen@linux.alibaba.com; NM=1; PH=DS; RN=17; SR=0; TI=SMTPD_---0Uv1Xg1-_1636023561; Received: from localhost.localdomain(mailfrom:xuesong.chen@linux.alibaba.com fp:SMTPD_---0Uv1Xg1-_1636023561) by smtp.aliyun-inc.com(127.0.0.1); Thu, 04 Nov 2021 18:59:22 +0800 From: Xuesong Chen To: helgaas@kernel.org Cc: catalin.marinas@arm.com, lorenzo.pieralisi@arm.com, james.morse@arm.com, will@kernel.org, rafael@kernel.org, tony.luck@intel.com, bp@alien8.de, mingo@kernel.org, bhelgaas@google.com, ying.huang@intel.com, linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, xuesong.chen@linux.alibaba.com Subject: [PATCH v5 1/4] PCI: MCFG: Consolidate the separate PCI MCFG table entry list Date: Thu, 4 Nov 2021 18:59:14 +0800 Message-Id: <20211104105914.47526-1-xuesong.chen@linux.alibaba.com> X-Mailer: git-send-email 2.24.3 (Apple Git-128) In-Reply-To: <20211104105715.47396-1-xuesong.chen@linux.alibaba.com> References: <20211104105715.47396-1-xuesong.chen@linux.alibaba.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211104_035936_626927_15AA06F4 X-CRM114-Status: GOOD ( 19.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The PCI MCFG entry list is redundant on x86 and other arches like ARM64 in current implementation, this list variable can be consolidated for unnecessary duplication and other purposes, for example, we can remove some of the arch-specific codes in the APEI/EINJ module and re-implement it in a more common arch-agnostic way. To reduce the redundancy, it: - Moves the "struct pci_mmcfg_region" definition from arch/x86/include/asm/pci_x86.h to include/linux/pci.h, where it can be shared across arches. - Moves pci_mmcfg_list (a list of pci_mmcfg_region structs) from arch/x86/pci/mmconfig-shared.c to drivers/pci/pci.c, where it can be shared across arches. - On x86 (which does not enable CONFIG_ACPI_MCFG), pci_mmcfg_list is built in arch/x86/pci/mmconfig-shared.c as before. - Removes the "struct mcfg_entry" from drivers/acpi/pci_mcfg.c. - Replaces pci_mcfg_list (previously a list of mcfg_entry structs) in drivers/acpi/pci_mcfg.c with the newly-shared pci_mmcfg_list (a list of pci_mmcfg_region structs). - On ARM64 (which does enable CONFIG_ACPI_MCFG), pci_mmcfg_list is built in drivers/acpi/pci_mcfg.c. Signed-off-by: Xuesong Chen --- arch/x86/include/asm/pci_x86.h | 17 +---------------- arch/x86/pci/mmconfig-shared.c | 2 -- drivers/acpi/pci_mcfg.c | 35 ++++++++++++++--------------------- drivers/pci/pci.c | 2 ++ include/linux/pci.h | 17 +++++++++++++++++ 5 files changed, 34 insertions(+), 39 deletions(-) diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 490411d..1f4257c 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -146,20 +146,7 @@ extern int pci_legacy_init(void); extern void pcibios_fixup_irqs(void); /* pci-mmconfig.c */ - -/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ -#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) - -struct pci_mmcfg_region { - struct list_head list; - struct resource res; - u64 address; - char __iomem *virt; - u16 segment; - u8 start_bus; - u8 end_bus; - char name[PCI_MMCFG_RESOURCE_NAME_LEN]; -}; +struct pci_mmcfg_region; extern int __init pci_mmcfg_arch_init(void); extern void __init pci_mmcfg_arch_free(void); @@ -174,8 +161,6 @@ extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, extern struct list_head pci_mmcfg_list; -#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) - /* * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use * %eax. No other source or target registers may be used. The following diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 758cbfe..0b961fe6 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -31,8 +31,6 @@ static bool pci_mmcfg_arch_init_failed; static DEFINE_MUTEX(pci_mmcfg_lock); #define pci_mmcfg_lock_held() lock_is_held(&(pci_mmcfg_lock).dep_map) -LIST_HEAD(pci_mmcfg_list); - static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) { if (cfg->res.parent) diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c index 53cab97..6ce467f 100644 --- a/drivers/acpi/pci_mcfg.c +++ b/drivers/acpi/pci_mcfg.c @@ -13,14 +13,7 @@ #include #include -/* Structure to hold entries from the MCFG table */ -struct mcfg_entry { - struct list_head list; - phys_addr_t addr; - u16 segment; - u8 bus_start; - u8 bus_end; -}; +extern struct list_head pci_mmcfg_list; #ifdef CONFIG_PCI_QUIRKS struct mcfg_fixup { @@ -214,16 +207,13 @@ static void pci_mcfg_apply_quirks(struct acpi_pci_root *root, #endif } -/* List to save MCFG entries */ -static LIST_HEAD(pci_mcfg_list); - int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, const struct pci_ecam_ops **ecam_ops) { const struct pci_ecam_ops *ops = &pci_generic_ecam_ops; struct resource *bus_res = &root->secondary; u16 seg = root->segment; - struct mcfg_entry *e; + struct pci_mmcfg_region *e; struct resource res; /* Use address from _CBA if present, otherwise lookup MCFG */ @@ -233,10 +223,10 @@ int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres, /* * We expect the range in bus_res in the coverage of MCFG bus range. */ - list_for_each_entry(e, &pci_mcfg_list, list) { - if (e->segment == seg && e->bus_start <= bus_res->start && - e->bus_end >= bus_res->end) { - root->mcfg_addr = e->addr; + list_for_each_entry(e, &pci_mmcfg_list, list) { + if (e->segment == seg && e->start_bus <= bus_res->start && + e->end_bus >= bus_res->end) { + root->mcfg_addr = e->address; } } @@ -268,7 +258,7 @@ static __init int pci_mcfg_parse(struct acpi_table_header *header) { struct acpi_table_mcfg *mcfg; struct acpi_mcfg_allocation *mptr; - struct mcfg_entry *e, *arr; + struct pci_mmcfg_region *e, *arr; int i, n; if (header->length < sizeof(struct acpi_table_mcfg)) @@ -285,10 +275,13 @@ static __init int pci_mcfg_parse(struct acpi_table_header *header) for (i = 0, e = arr; i < n; i++, mptr++, e++) { e->segment = mptr->pci_segment; - e->addr = mptr->address; - e->bus_start = mptr->start_bus_number; - e->bus_end = mptr->end_bus_number; - list_add(&e->list, &pci_mcfg_list); + e->address = mptr->address; + e->start_bus = mptr->start_bus_number; + e->end_bus = mptr->end_bus_number; + e->res.start = e->address + PCI_MMCFG_BUS_OFFSET(e->start_bus); + e->res.end = e->address + PCI_MMCFG_BUS_OFFSET(e->end_bus + 1) - 1; + e->res.flags = IORESOURCE_MEM | IORESOURCE_BUSY; + list_add(&e->list, &pci_mmcfg_list); } #ifdef CONFIG_PCI_QUIRKS diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index f2cd111..29ddfdd 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -47,6 +47,8 @@ EXPORT_SYMBOL(isa_dma_bridge_buggy); int pci_pci_problems; EXPORT_SYMBOL(pci_pci_problems); +LIST_HEAD(pci_mmcfg_list); + unsigned int pci_pm_d3hot_delay; static void pci_pme_list_scan(struct work_struct *work); diff --git a/include/linux/pci.h b/include/linux/pci.h index c8afbee..af8dcc8 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -55,6 +55,23 @@ #define PCI_RESET_PROBE true #define PCI_RESET_DO_RESET false +#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) + +/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ +#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) + +/* pci mcfg region */ +struct pci_mmcfg_region { + struct list_head list; + struct resource res; + u64 address; + char __iomem *virt; + u16 segment; + u8 start_bus; + u8 end_bus; + char name[PCI_MMCFG_RESOURCE_NAME_LEN]; +}; + /* * The PCI interface treats multi-function devices as independent * devices. The slot/function address of each device is encoded