| Message ID | 20211105134228.731331-2-aford173@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/5] soc: imx: imx8m-blk-ctrl: Fix imx8mm mipi reset | expand |
On Fri, Nov 5, 2021 at 6:42 AM Adam Ford <aford173@gmail.com> wrote: > > There is a csi bridge and csis interface that tie together > to allow csi2 capture. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > --- > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 51 +++++++++++++++++++++++ > 1 file changed, 51 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index c2f3f118f82e..1f69c14d953f 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1068,6 +1068,22 @@ aips4: bus@32c00000 { > #size-cells = <1>; > ranges = <0x32c00000 0x32c00000 0x400000>; > > + csi: csi@32e20000 { > + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; > + reg = <0x32e20000 0x1000>; > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; > + clock-names = "mclk"; > + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; > + status = "disabled"; > + > + port { > + csi_in: endpoint { > + remote-endpoint = <&imx8mm_mipi_csi_out>; > + }; > + }; > + }; > + > disp_blk_ctrl: blk-ctrl@32e28000 { > compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; > reg = <0x32e28000 0x100>; > @@ -1095,6 +1111,41 @@ disp_blk_ctrl: blk-ctrl@32e28000 { > #power-domain-cells = <1>; > }; > > + mipi_csi: mipi-csi@32e30000 { > + compatible = "fsl,imx8mm-mipi-csi2"; > + reg = <0x32e30000 0x1000>; > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; > + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, > + <&clk IMX8MM_CLK_CSI1_PHY_REF>; > + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, > + <&clk IMX8MM_SYS_PLL2_1000M>; > + clock-frequency = <333000000>; > + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, > + <&clk IMX8MM_CLK_CSI1_ROOT>, > + <&clk IMX8MM_CLK_CSI1_PHY_REF>, > + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; > + clock-names = "pclk", "wrap", "phy", "axi"; > + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + }; > + > + port@1 { > + reg = <1>; > + > + imx8mm_mipi_csi_out: endpoint { > + remote-endpoint = <&csi_in>; > + }; > + }; > + }; > + }; > + > usbotg1: usb@32e40000 { > compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; > reg = <0x32e40000 0x200>; > -- > 2.32.0 > Adam, With your new series I can also now capture without hanging from imx219 on imx8mm-venice-gw73xx-0x: media-ctl --links "'imx219 2-0010':0->'imx7-mipi-csis.0':0[1]" media-ctl -v -V "'imx219 2-0010':0 [fmt:SRGGB8/640x480 field:none]" media-ctl -v -V "'csi':0 [fmt:SRGGB8/640x480 field:none]" media-ctl --print-topology gst-launch-1.0 -v v4l2src num-buffers=1 ! video/x-bayer,format=rggb,width=640,height=480,framerate=30/1 ! filesink location=test.raw # not sure how to view this gst-launch-1.0 -v v4l2src num-buffers=1 ! video/x-bayer,format=rggb,width=640,height=480,framerate=30/1 ! bayer2rgb ! filesink location=test.rgb # not sure how to view this gst-launch-1.0 -v v4l2src num-buffers=1 ! video/x-bayer,format=rggb,width=640,height=480,framerate=30/1 ! bayer2rgb ! jpegenc ! filesink location=test.jpg # works - image is good gst-launch-1.0 -v v4l2src num-buffers=300 ! video/x-bayer,format=rggb,width=640,height=480,framerate=30/1 ! bayer2rgb ! jpegenc ! avimux ! filesink location=test.avi # works -image is good Thanks for your work on this! For the series: Reviewed-By: Tim Harvey <tharvey@gateworks.com> Tested-By: Tim Harvey <tharvey@gateworks.com> (imx8mm-venice-gw73xx-0x + rpiv2 IMX219 camera) Best regards, Tim
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index c2f3f118f82e..1f69c14d953f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1068,6 +1068,22 @@ aips4: bus@32c00000 { #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + csi: csi@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx7-csi"; + reg = <0x32e20000 0x1000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + clock-names = "mclk"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>; + status = "disabled"; + + port { + csi_in: endpoint { + remote-endpoint = <&imx8mm_mipi_csi_out>; + }; + }; + }; + disp_blk_ctrl: blk-ctrl@32e28000 { compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; reg = <0x32e28000 0x100>; @@ -1095,6 +1111,41 @@ disp_blk_ctrl: blk-ctrl@32e28000 { #power-domain-cells = <1>; }; + mipi_csi: mipi-csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi2"; + reg = <0x32e30000 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL2_1000M>; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + clock-names = "pclk", "wrap", "phy", "axi"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + imx8mm_mipi_csi_out: endpoint { + remote-endpoint = <&csi_in>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>;