| Message ID | 20211112063155.3485777-1-peng.fan@oss.nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: k3-j721e: correct cache-sets info | expand |
On 14:31-20211112, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache > - ICache is 3-way set-associative > - Dcache is 2-way set-associative > - Line size are 64bytes > > So correct the cache-sets info. > > Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC") > Signed-off-by: Peng Fan <peng.fan@nxp.com> > --- > arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > index 214359e7288b..a5967ba139d7 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi > @@ -64,7 +64,7 @@ cpu0: cpu@0 { > i-cache-sets = <256>; > d-cache-size = <0x8000>; > d-cache-line-size = <64>; > - d-cache-sets = <128>; > + d-cache-sets = <256>; > next-level-cache = <&L2_0>; > }; > > @@ -78,7 +78,7 @@ cpu1: cpu@1 { > i-cache-sets = <256>; > d-cache-size = <0x8000>; > d-cache-line-size = <64>; > - d-cache-sets = <128>; > + d-cache-sets = <256>; > next-level-cache = <&L2_0>; > }; > }; > -- > 2.25.1 > Arrgh.. Thank you for fixing this. Reviewed-by: Nishanth Menon <nm@ti.com> I think J7200 also needs fixups. Will cross check and post additional patches depending on the ones that need it.
On 14:31-20211112, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
Minor comment (should be easy to fix when picking up the patch), lest I
forget-> $subject: arm64: dts: ti: to maintain consistency
Hi Peng Fan (OSS), On Fri, 12 Nov 2021 14:31:55 +0800, Peng Fan (OSS) wrote: > From: Peng Fan <peng.fan@nxp.com> > > A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache > - ICache is 3-way set-associative > - Dcache is 2-way set-associative > - Line size are 64bytes > > [...] I have applied the following to branch ti-k3-dts-next on [1]. Fixed $subject as suggested by Nishanth. Thank you! [1/1] arm64: dts: k3-j721e: correct cache-sets info commit: 7a0df1f969c14939f60a7f9a6af72adcc314675f All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Vignesh
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 214359e7288b..a5967ba139d7 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -64,7 +64,7 @@ cpu0: cpu@0 { i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -78,7 +78,7 @@ cpu1: cpu@1 { i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; };