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Fri, 12 Nov 2021 05:12:37 -0800 (PST) Received: from localhost ([193.209.96.43]) by smtp.gmail.com with ESMTPSA id h18sm6276740wre.46.2021.11.12.05.12.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Nov 2021 05:12:36 -0800 (PST) From: Thierry Reding To: Joerg Roedel , Will Deacon , Robin Murphy , Rob Herring Cc: Thierry Reding , Jon Hunter , iommu@lists.linux-foundation.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/4] dt-bindings: arm-smmu: Document nvidia, memory-controller property Date: Fri, 12 Nov 2021 14:12:28 +0100 Message-Id: <20211112131231.3683098-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211112131231.3683098-1-thierry.reding@gmail.com> References: <20211112131231.3683098-1-thierry.reding@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211112_051238_716596_AA2FBC0E X-CRM114-Status: GOOD ( 11.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Thierry Reding On NVIDIA SoC's the ARM SMMU needs to interact with the memory controller in order to map memory clients to the corresponding stream IDs. Document how the nvidia,memory-controller property can be used to achieve this. Signed-off-by: Thierry Reding --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index f66a3effba73..cf32a7955475 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -155,6 +155,12 @@ properties: power-domains: maxItems: 1 + nvidia,memory-controller: + description: A phandle to the memory controller on NVIDIA Tegra186 + and later SoCs. The memory controller needs to be programmed with + a mapping of memory client IDs to ARM SMMU stream IDs. + $ref: /schemas/types.yaml#/definitions/phandle + required: - compatible - reg @@ -177,6 +183,9 @@ allOf: reg: minItems: 1 maxItems: 2 + + required: + - nvidia,memory-controller else: properties: reg: