| Message ID | 20211122104616.537156-4-boger@wirenboard.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add support for Allwinner R40 CAN controller | expand |
Hi, On Mon, Nov 22, 2021 at 01:46:16PM +0300, Evgeny Boger wrote: > Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The > controller is the same as in earlier A10 and A20 SoCs, but needs reset > line to be deasserted before use. > > This patch adds a CAN node and the corresponding pinctrl descriptions. > > Signed-off-by: Evgeny Boger <boger@wirenboard.com> > --- > arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi > index 1d87fc0c24ee..c99c92f008a0 100644 > --- a/arch/arm/boot/dts/sun8i-r40.dtsi > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi > @@ -511,6 +511,16 @@ pio: pinctrl@1c20800 { > #interrupt-cells = <3>; > #gpio-cells = <3>; > > + can_ph_pins: can-ph-pins { > + pins = "PH20", "PH21"; > + function = "can"; > + }; > + > + can_pa_pins: can-pa-pins { > + pins = "PA16", "PA17"; > + function = "can"; > + }; > + These nodes should be ordered alphabetically Also, we should mark them with /omit-if-no-ref/ to remove them from the DT if they are not referenced anywhere else in the DT. Maxime > clk_out_a_pin: clk-out-a-pin { > pins = "PI12"; > function = "clk_out_a"; > @@ -926,6 +936,15 @@ i2c3: i2c@1c2b800 { > #size-cells = <0>; > }; > > + can0: can@1c2bc00 { > + compatible = "allwinner,sun8i-r40-can"; > + reg = <0x01c2bc00 0x400>; > + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CAN>; > + resets = <&ccu RST_BUS_CAN>; > + status = "disabled"; > + }; > + > i2c4: i2c@1c2c000 { > compatible = "allwinner,sun6i-a31-i2c"; > reg = <0x01c2c000 0x400>; > -- > 2.25.1 >
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi index 1d87fc0c24ee..c99c92f008a0 100644 --- a/arch/arm/boot/dts/sun8i-r40.dtsi +++ b/arch/arm/boot/dts/sun8i-r40.dtsi @@ -511,6 +511,16 @@ pio: pinctrl@1c20800 { #interrupt-cells = <3>; #gpio-cells = <3>; + can_ph_pins: can-ph-pins { + pins = "PH20", "PH21"; + function = "can"; + }; + + can_pa_pins: can-pa-pins { + pins = "PA16", "PA17"; + function = "can"; + }; + clk_out_a_pin: clk-out-a-pin { pins = "PI12"; function = "clk_out_a"; @@ -926,6 +936,15 @@ i2c3: i2c@1c2b800 { #size-cells = <0>; }; + can0: can@1c2bc00 { + compatible = "allwinner,sun8i-r40-can"; + reg = <0x01c2bc00 0x400>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CAN>; + resets = <&ccu RST_BUS_CAN>; + status = "disabled"; + }; + i2c4: i2c@1c2c000 { compatible = "allwinner,sun6i-a31-i2c"; reg = <0x01c2c000 0x400>;
Allwinner R40 (also known as A40i, T3, V40) has a CAN controller. The controller is the same as in earlier A10 and A20 SoCs, but needs reset line to be deasserted before use. This patch adds a CAN node and the corresponding pinctrl descriptions. Signed-off-by: Evgeny Boger <boger@wirenboard.com> --- arch/arm/boot/dts/sun8i-r40.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)