| Message ID | 20211125211443.1150135-13-Mr.Bossman075@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add initial support for the i.MXRTxxxx SoC family starting from i.IMXRT1050 SoC. | expand |
On Thu, Nov 25, 2021 at 04:14:42PM -0500, Jesse Taube wrote: > From: Giulio Benetti <giulio.benetti@benettiengineering.com> > > The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid > evaluation of the i.MXRT, which features NXP's implementation of the Arm > Cortex-M7 core. > > The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, > USB 2.0 OTG. > > This patch aims to support the preliminary booting up features > as follows: > GPIO > LPUART > SD/MMC > > Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> > Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> > [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] > --- > V1->V2: > * dtsi: Add clock parent definitions > * dtsi: Change hex values to lowercase > * dtsi: Move anatop definition from driver > * dts: Remove unused pin controll (semc) > * dts: Use moved pin controll header > * Move aliases from dtsi to dts > * Change commit description > * Change licence to "GPL-2.0+ OR MIT" > V2->V3: > * Remove bootargs, comments, unused container > * Remove unnecessary new lines > * Rename imxrt to imxrt1050 for seiral and mmc > * GPT uses own clock > * fix memory@0 > * Change GPT compatible handles > --- > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imxrt1050-evk.dts | 72 ++++++++++++ > arch/arm/boot/dts/imxrt1050.dtsi | 165 ++++++++++++++++++++++++++++ > 3 files changed, 239 insertions(+) > create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts > create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 8a2dfdf01ce3..d539bf7daa86 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -723,6 +723,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ > dtb-$(CONFIG_SOC_IMX7ULP) += \ > imx7ulp-com.dtb \ > imx7ulp-evk.dtb > +dtb-$(CONFIG_SOC_IMXRT) += \ > + imxrt1050-evk.dtb > dtb-$(CONFIG_SOC_LS1021A) += \ > ls1021a-moxa-uc-8410a.dtb \ > ls1021a-qds.dtb \ > diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts > new file mode 100644 > index 000000000000..6a9c10decf52 > --- /dev/null > +++ b/arch/arm/boot/dts/imxrt1050-evk.dts > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 > + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > + > +/dts-v1/; > +#include "imxrt1050.dtsi" > +#include "imxrt1050-pinfunc.h" > + > +/ { > + model = "NXP IMXRT1050-evk board"; > + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; > + > + chosen { > + stdout-path = &lpuart1; > + }; > + > + aliases { > + gpio0 = &gpio1; > + gpio1 = &gpio2; > + gpio2 = &gpio3; > + gpio3 = &gpio4; > + gpio4 = &gpio5; > + mmc0 = &usdhc1; > + serial0 = &lpuart1; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x80000000 0x2000000>; > + }; > +}; > + > +&lpuart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lpuart1>; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl_lpuart1: lpuart1grp { > + fsl,pins = < > + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 > + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 > + >; > + }; > + > + pinctrl_usdhc0: usdhc0grp { > + fsl,pins = < > + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 > + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 > + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 > + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 > + >; > + }; > +}; > + > +&usdhc1 { > + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; > + pinctrl-0 = <&pinctrl_usdhc0>; > + pinctrl-1 = <&pinctrl_usdhc0>; > + pinctrl-2 = <&pinctrl_usdhc0>; > + pinctrl-3 = <&pinctrl_usdhc0>; > + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi > new file mode 100644 > index 000000000000..35943a6896fa > --- /dev/null > +++ b/arch/arm/boot/dts/imxrt1050.dtsi > @@ -0,0 +1,165 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2019 > + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> > + */ > + > +#include "armv7-m.dtsi" > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/imxrt1050-clock.h> > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + > + clocks { > + osc: osc { > + compatible = "fsl,imx-osc", "fixed-clock"; fsl,imx-osc is not documented. IMO, just drop it. > + #clock-cells = <0>; > + clock-frequency = <24000000>; > + }; > + }; > + > + cpus { > + #address-cells = <0x01>; > + #size-cells = <0x00>; > + > + cpu@0 { > + compatible = "arm,cortex-m7"; Not documented. Please run schema validation checks and don't add any new warnings not already present for i.MX. > + device_type = "cpu"; > + reg = <0x00>; > + }; > + }; > + > + soc { > + lpuart1: serial@40184000 { > + compatible = "fsl,imxrt1050-lpuart","fsl,imx8mm-uart", "fsl,imx6q-uart"; space ^ > + reg = <0x40184000 0x4000>; > + interrupts = <20>; > + clocks = <&clks IMXRT1050_CLK_LPUART1>; > + clock-names = "ipg"; > + status = "disabled"; > + }; > + > + iomuxc: iomuxc@401f8000 { pinctrl@... > + compatible = "fsl,imxrt1050-iomuxc"; > + reg = <0x401f8000 0x4000>; > + fsl,mux_mask = <0x7>; > + }; > + > + anatop: anatop@400d8000 { > + compatible = "fsl,imxrt-anatop"; > + reg = <0x400d8000 0x4000>; > + }; > + > + clks: ccm@400fc000 { clock-controller@... > + compatible = "fsl,imxrt1050-ccm"; > + reg = <0x400fc000 0x4000>; > + interrupts = <95>, <96>; > + clocks = <&osc>; > + clock-names = "osc"; > + #clock-cells = <1>; > + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, > + <&clks IMXRT1050_CLK_PLL1_BYPASS>, > + <&clks IMXRT1050_CLK_PLL2_BYPASS>, > + <&clks IMXRT1050_CLK_PLL3_BYPASS>, > + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, > + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; > + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, > + <&clks IMXRT1050_CLK_PLL1_ARM>, > + <&clks IMXRT1050_CLK_PLL2_SYS>, > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, > + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, > + <&clks IMXRT1050_CLK_PLL2_SYS>; > + }; > + > + edma1: dma-controller@400e8000 { > + #dma-cells = <2>; > + compatible = "fsl,imx7ulp-edma"; > + reg = <0x400e8000 0x4000>, > + <0x400ec000 0x4000>; > + dma-channels = <32>; > + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, > + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; > + clock-names = "dma", "dmamux0"; > + clocks = <&clks IMXRT1050_CLK_DMA>, > + <&clks IMXRT1050_CLK_DMA_MUX>; > + }; > + > + usdhc1: mmc@402c0000 { > + compatible ="fsl,imxrt1050-usdhc"; > + reg = <0x402c0000 0x4000>; > + interrupts = <110>; > + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, > + <&clks IMXRT1050_CLK_OSC>, > + <&clks IMXRT1050_CLK_USDHC1>; > + clock-names = "ipg", "ahb", "per"; > + bus-width = <4>; > + fsl,wp-controller; > + no-1-8-v; > + max-frequency = <4000000>; > + fsl,tuning-start-tap = <20>; > + fsl,tuning-step= <2>; > + status = "disabled"; > + }; > + > + gpio1: gpio@401b8000 { > + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; Not SoC specific? > + reg = <0x401b8000 0x4000>; > + interrupts = <80>, <81>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio2: gpio@401bc000 { > + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; > + reg = <0x401bc000 0x4000>; > + interrupts = <82>, <83>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio3: gpio@401c0000 { > + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; > + reg = <0x401c0000 0x4000>; > + interrupts = <84>, <85>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio4: gpio@401c4000 { > + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; > + reg = <0x401c4000 0x4000>; > + interrupts = <86>, <87>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpio5: gpio@400c0000 { > + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; > + reg = <0x400c0000 0x4000>; > + interrupts = <88>, <89>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + gpt: timer@401ec000 { > + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; > + reg = <0x401ec000 0x4000>; > + interrupts = <100>; > + clocks = <&clks IMXRT1050_CLK_GPT>; > + clock-names = "per"; > + }; > + }; > +}; > -- > 2.34.0 > >
On 11/28/21 11:43, Rob Herring wrote: > On Thu, Nov 25, 2021 at 04:14:42PM -0500, Jesse Taube wrote: >> From: Giulio Benetti <giulio.benetti@benettiengineering.com> >> >> The NXP i.MXRT1050 Evaluation Kit (EVK) provides a platform for rapid >> evaluation of the i.MXRT, which features NXP's implementation of the Arm >> Cortex-M7 core. >> >> The EVK provides 32 MB SDRAM, 64 MB Quad SPI flash, Micro SD card socket, >> USB 2.0 OTG. >> >> This patch aims to support the preliminary booting up features >> as follows: >> GPIO >> LPUART >> SD/MMC >> >> Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> >> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com> >> [Jesse: Add clock-parents, edma, usdhc, anatop, remove old pinctl] >> --- >> V1->V2: >> * dtsi: Add clock parent definitions >> * dtsi: Change hex values to lowercase >> * dtsi: Move anatop definition from driver >> * dts: Remove unused pin controll (semc) >> * dts: Use moved pin controll header >> * Move aliases from dtsi to dts >> * Change commit description >> * Change licence to "GPL-2.0+ OR MIT" >> V2->V3: >> * Remove bootargs, comments, unused container >> * Remove unnecessary new lines >> * Rename imxrt to imxrt1050 for seiral and mmc >> * GPT uses own clock >> * fix memory@0 >> * Change GPT compatible handles >> --- >> arch/arm/boot/dts/Makefile | 2 + >> arch/arm/boot/dts/imxrt1050-evk.dts | 72 ++++++++++++ >> arch/arm/boot/dts/imxrt1050.dtsi | 165 ++++++++++++++++++++++++++++ >> 3 files changed, 239 insertions(+) >> create mode 100644 arch/arm/boot/dts/imxrt1050-evk.dts >> create mode 100644 arch/arm/boot/dts/imxrt1050.dtsi >> >> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile >> index 8a2dfdf01ce3..d539bf7daa86 100644 >> --- a/arch/arm/boot/dts/Makefile >> +++ b/arch/arm/boot/dts/Makefile >> @@ -723,6 +723,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ >> dtb-$(CONFIG_SOC_IMX7ULP) += \ >> imx7ulp-com.dtb \ >> imx7ulp-evk.dtb >> +dtb-$(CONFIG_SOC_IMXRT) += \ >> + imxrt1050-evk.dtb >> dtb-$(CONFIG_SOC_LS1021A) += \ >> ls1021a-moxa-uc-8410a.dtb \ >> ls1021a-qds.dtb \ >> diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts >> new file mode 100644 >> index 000000000000..6a9c10decf52 >> --- /dev/null >> +++ b/arch/arm/boot/dts/imxrt1050-evk.dts >> @@ -0,0 +1,72 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 >> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> >> + */ >> + >> +/dts-v1/; >> +#include "imxrt1050.dtsi" >> +#include "imxrt1050-pinfunc.h" >> + >> +/ { >> + model = "NXP IMXRT1050-evk board"; >> + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; >> + >> + chosen { >> + stdout-path = &lpuart1; >> + }; >> + >> + aliases { >> + gpio0 = &gpio1; >> + gpio1 = &gpio2; >> + gpio2 = &gpio3; >> + gpio3 = &gpio4; >> + gpio4 = &gpio5; >> + mmc0 = &usdhc1; >> + serial0 = &lpuart1; >> + }; >> + >> + memory@80000000 { >> + device_type = "memory"; >> + reg = <0x80000000 0x2000000>; >> + }; >> +}; >> + >> +&lpuart1 { >> + pinctrl-names = "default"; >> + pinctrl-0 = <&pinctrl_lpuart1>; >> + status = "okay"; >> +}; >> + >> +&iomuxc { >> + pinctrl-names = "default"; >> + pinctrl_lpuart1: lpuart1grp { >> + fsl,pins = < >> + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 >> + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 >> + >; >> + }; >> + >> + pinctrl_usdhc0: usdhc0grp { >> + fsl,pins = < >> + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 >> + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 >> + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 >> + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 >> + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 >> + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 >> + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 >> + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 >> + >; >> + }; >> +}; >> + >> +&usdhc1 { >> + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; >> + pinctrl-0 = <&pinctrl_usdhc0>; >> + pinctrl-1 = <&pinctrl_usdhc0>; >> + pinctrl-2 = <&pinctrl_usdhc0>; >> + pinctrl-3 = <&pinctrl_usdhc0>; >> + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; >> + status = "okay"; >> +}; >> diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi >> new file mode 100644 >> index 000000000000..35943a6896fa >> --- /dev/null >> +++ b/arch/arm/boot/dts/imxrt1050.dtsi >> @@ -0,0 +1,165 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 >> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> >> + */ >> + >> +#include "armv7-m.dtsi" >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/imxrt1050-clock.h> >> +#include <dt-bindings/gpio/gpio.h> >> + >> +/ { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + clocks { >> + osc: osc { >> + compatible = "fsl,imx-osc", "fixed-clock"; > > fsl,imx-osc is not documented. IMO, just drop it. Other imx device trees have it, should i still? > >> + #clock-cells = <0>; >> + clock-frequency = <24000000>; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <0x01>; >> + #size-cells = <0x00>; >> + >> + cpu@0 { >> + compatible = "arm,cortex-m7"; > > Not documented. > > Please run schema validation checks and don't add any new warnings not > already present for i.MX. Ah sorry was from u-boot. > >> + device_type = "cpu"; >> + reg = <0x00>; >> + }; >> + }; >> + >> + soc { >> + lpuart1: serial@40184000 { >> + compatible = "fsl,imxrt1050-lpuart","fsl,imx8mm-uart", "fsl,imx6q-uart"; > > space ^ > >> + reg = <0x40184000 0x4000>; >> + interrupts = <20>; >> + clocks = <&clks IMXRT1050_CLK_LPUART1>; >> + clock-names = "ipg"; >> + status = "disabled"; >> + }; >> + >> + iomuxc: iomuxc@401f8000 { > > pinctrl@... > >> + compatible = "fsl,imxrt1050-iomuxc"; >> + reg = <0x401f8000 0x4000>; >> + fsl,mux_mask = <0x7>; >> + }; >> + >> + anatop: anatop@400d8000 { >> + compatible = "fsl,imxrt-anatop"; >> + reg = <0x400d8000 0x4000>; >> + }; >> + >> + clks: ccm@400fc000 { > > clock-controller@... > >> + compatible = "fsl,imxrt1050-ccm"; >> + reg = <0x400fc000 0x4000>; >> + interrupts = <95>, <96>; >> + clocks = <&osc>; >> + clock-names = "osc"; >> + #clock-cells = <1>; >> + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, >> + <&clks IMXRT1050_CLK_PLL1_BYPASS>, >> + <&clks IMXRT1050_CLK_PLL2_BYPASS>, >> + <&clks IMXRT1050_CLK_PLL3_BYPASS>, >> + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, >> + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; >> + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, >> + <&clks IMXRT1050_CLK_PLL1_ARM>, >> + <&clks IMXRT1050_CLK_PLL2_SYS>, >> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, >> + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, >> + <&clks IMXRT1050_CLK_PLL2_SYS>; >> + }; >> + >> + edma1: dma-controller@400e8000 { >> + #dma-cells = <2>; >> + compatible = "fsl,imx7ulp-edma"; >> + reg = <0x400e8000 0x4000>, >> + <0x400ec000 0x4000>; >> + dma-channels = <32>; >> + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, >> + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; >> + clock-names = "dma", "dmamux0"; >> + clocks = <&clks IMXRT1050_CLK_DMA>, >> + <&clks IMXRT1050_CLK_DMA_MUX>; >> + }; >> + >> + usdhc1: mmc@402c0000 { >> + compatible ="fsl,imxrt1050-usdhc"; >> + reg = <0x402c0000 0x4000>; >> + interrupts = <110>; >> + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, >> + <&clks IMXRT1050_CLK_OSC>, >> + <&clks IMXRT1050_CLK_USDHC1>; >> + clock-names = "ipg", "ahb", "per"; >> + bus-width = <4>; >> + fsl,wp-controller; >> + no-1-8-v; >> + max-frequency = <4000000>; >> + fsl,tuning-start-tap = <20>; >> + fsl,tuning-step= <2>; >> + status = "disabled"; >> + }; >> + >> + gpio1: gpio@401b8000 { >> + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; > > Not SoC specific? fsl,imxrt-gpio is a placeholder, it is compatible with imx35. > >> + reg = <0x401b8000 0x4000>; >> + interrupts = <80>, <81>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio2: gpio@401bc000 { >> + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; >> + reg = <0x401bc000 0x4000>; >> + interrupts = <82>, <83>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio3: gpio@401c0000 { >> + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; >> + reg = <0x401c0000 0x4000>; >> + interrupts = <84>, <85>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio4: gpio@401c4000 { >> + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; >> + reg = <0x401c4000 0x4000>; >> + interrupts = <86>, <87>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpio5: gpio@400c0000 { >> + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; >> + reg = <0x400c0000 0x4000>; >> + interrupts = <88>, <89>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + gpt: timer@401ec000 { >> + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; >> + reg = <0x401ec000 0x4000>; >> + interrupts = <100>; >> + clocks = <&clks IMXRT1050_CLK_GPT>; >> + clock-names = "per"; >> + }; >> + }; >> +}; >> -- >> 2.34.0 >> >>
Hi Rob, Jesse, On 28/11/21 17:43, Rob Herring wrote: [SNIP] >> diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi >> new file mode 100644 >> index 000000000000..35943a6896fa >> --- /dev/null >> +++ b/arch/arm/boot/dts/imxrt1050.dtsi >> @@ -0,0 +1,165 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (C) 2019 >> + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> >> + */ >> + >> +#include "armv7-m.dtsi" >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/imxrt1050-clock.h> >> +#include <dt-bindings/gpio/gpio.h> >> + >> +/ { >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + clocks { >> + osc: osc { >> + compatible = "fsl,imx-osc", "fixed-clock"; > > fsl,imx-osc is not documented. IMO, just drop it. Regarding this ^^^, you're right, so we avoid to add "fsl,imx-osc", but at this point, does it make sense we create a patchset to remove it from the other .dts(i) files that use it? And same goes for "fsl,imx-ckil", "fsl,imx-ckih1", "fsl,imx-ckih2"? I see that those try to repeat the name of the node itself so they are useless. If you say so I send a patchset for that. Thank you Best regards
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8a2dfdf01ce3..d539bf7daa86 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -723,6 +723,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-com.dtb \ imx7ulp-evk.dtb +dtb-$(CONFIG_SOC_IMXRT) += \ + imxrt1050-evk.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-moxa-uc-8410a.dtb \ ls1021a-qds.dtb \ diff --git a/arch/arm/boot/dts/imxrt1050-evk.dts b/arch/arm/boot/dts/imxrt1050-evk.dts new file mode 100644 index 000000000000..6a9c10decf52 --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050-evk.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +/dts-v1/; +#include "imxrt1050.dtsi" +#include "imxrt1050-pinfunc.h" + +/ { + model = "NXP IMXRT1050-evk board"; + compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + mmc0 = &usdhc1; + serial0 = &lpuart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x2000000>; + }; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD 0xf1 + MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD 0xf1 + >; + }; + + pinctrl_usdhc0: usdhc0grp { + fsl,pins = < + MXRT1050_IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x1B000 + MXRT1050_IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0xB069 + MXRT1050_IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x17061 + MXRT1050_IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x17061 + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0>; + pinctrl-1 = <&pinctrl_usdhc0>; + pinctrl-2 = <&pinctrl_usdhc0>; + pinctrl-3 = <&pinctrl_usdhc0>; + cd-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi new file mode 100644 index 000000000000..35943a6896fa --- /dev/null +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 + * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> + */ + +#include "armv7-m.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/imxrt1050-clock.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + clocks { + osc: osc { + compatible = "fsl,imx-osc", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + }; + + cpus { + #address-cells = <0x01>; + #size-cells = <0x00>; + + cpu@0 { + compatible = "arm,cortex-m7"; + device_type = "cpu"; + reg = <0x00>; + }; + }; + + soc { + lpuart1: serial@40184000 { + compatible = "fsl,imxrt1050-lpuart","fsl,imx8mm-uart", "fsl,imx6q-uart"; + reg = <0x40184000 0x4000>; + interrupts = <20>; + clocks = <&clks IMXRT1050_CLK_LPUART1>; + clock-names = "ipg"; + status = "disabled"; + }; + + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + fsl,mux_mask = <0x7>; + }; + + anatop: anatop@400d8000 { + compatible = "fsl,imxrt-anatop"; + reg = <0x400d8000 0x4000>; + }; + + clks: ccm@400fc000 { + compatible = "fsl,imxrt1050-ccm"; + reg = <0x400fc000 0x4000>; + interrupts = <95>, <96>; + clocks = <&osc>; + clock-names = "osc"; + #clock-cells = <1>; + assigned-clocks = <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL1_BYPASS>, + <&clks IMXRT1050_CLK_PLL2_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_BYPASS>, + <&clks IMXRT1050_CLK_PLL3_PFD1_664_62M>, + <&clks IMXRT1050_CLK_PLL2_PFD2_396M>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL1_REF_SEL>, + <&clks IMXRT1050_CLK_PLL1_ARM>, + <&clks IMXRT1050_CLK_PLL2_SYS>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL3_USB_OTG>, + <&clks IMXRT1050_CLK_PLL2_SYS>; + }; + + edma1: dma-controller@400e8000 { + #dma-cells = <2>; + compatible = "fsl,imx7ulp-edma"; + reg = <0x400e8000 0x4000>, + <0x400ec000 0x4000>; + dma-channels = <32>; + interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, + <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>; + clock-names = "dma", "dmamux0"; + clocks = <&clks IMXRT1050_CLK_DMA>, + <&clks IMXRT1050_CLK_DMA_MUX>; + }; + + usdhc1: mmc@402c0000 { + compatible ="fsl,imxrt1050-usdhc"; + reg = <0x402c0000 0x4000>; + interrupts = <110>; + clocks = <&clks IMXRT1050_CLK_IPG_PDOF>, + <&clks IMXRT1050_CLK_OSC>, + <&clks IMXRT1050_CLK_USDHC1>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + fsl,wp-controller; + no-1-8-v; + max-frequency = <4000000>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + gpio1: gpio@401b8000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401b8000 0x4000>; + interrupts = <80>, <81>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@401bc000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401bc000 0x4000>; + interrupts = <82>, <83>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@401c0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401c0000 0x4000>; + interrupts = <84>, <85>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@401c4000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x401c4000 0x4000>; + interrupts = <86>, <87>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <88>, <89>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt: timer@401ec000 { + compatible = "fsl,imxrt1050-gpt", "fsl,imx6dl-gpt", "fsl,imx6sl-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&clks IMXRT1050_CLK_GPT>; + clock-names = "per"; + }; + }; +};