diff mbox series

[V4,8/9] arm64: dts: imx8mn: add DISP blk-ctrl

Message ID 20211128131853.15125-9-aford173@gmail.com (mailing list archive)
State New, archived
Headers show
Series arm64: imx8mn: Enable more imx8m Nano functions | expand

Commit Message

Adam Ford Nov. 28, 2021, 1:18 p.m. UTC
Add the DT node for the DISP blk-ctrl. With this in place the
display/mipi power domains should be functional.

Signed-off-by: Adam Ford <aford173@gmail.com>
---
 arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
 1 file changed, 28 insertions(+)

--
2.32.0

Comments

Lucas Stach Dec. 14, 2021, 9:19 a.m. UTC | #1
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford:
> Add the DT node for the DISP blk-ctrl. With this in place the
> display/mipi power domains should be functional.
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 902d5725dc55..d8726d0ce326 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1039,6 +1039,34 @@ aips4: bus@32c00000 {
>  			#size-cells = <1>;
>  			ranges;
> 
> +			disp_blk_ctrl: blk-ctrl@32e28000 {
> +				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
> +				reg = <0x32e28000 0x100>;
> +				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
> +						<&pgc_dispmix>, <&pgc_mipi>,
> +						<&pgc_mipi>;
> +				power-domain-names = "bus", "isi",
> +						     "lcdif", "mipi-dsi",
> +						     "mipi-csi";
> +				clocks = <&clk IMX8MN_CLK_DISP_AXI>,
> +					 <&clk IMX8MN_CLK_DISP_APB>,
> +					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> +					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> +					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
> +					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
> +					 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
> +					 <&clk IMX8MN_CLK_DSI_CORE>,
> +					 <&clk IMX8MN_CLK_DSI_PHY_REF>,
> +					 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
> +					 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
> +				clock-names = "disp_axi", "disp_apb",
> +					      "disp_axi_root", "disp_apb_root",
> +					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
> +					      "dsi-pclk", "dsi-ref",
> +					      "csi-aclk", "csi-pclk";
> +				#power-domain-cells = <1>;
> +			};
> +
>  			usbotg1: usb@32e40000 {
>  				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
>  				reg = <0x32e40000 0x200>;
> --
> 2.32.0
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 902d5725dc55..d8726d0ce326 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -1039,6 +1039,34 @@  aips4: bus@32c00000 {
 			#size-cells = <1>;
 			ranges;

+			disp_blk_ctrl: blk-ctrl@32e28000 {
+				compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
+				reg = <0x32e28000 0x100>;
+				power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
+						<&pgc_dispmix>, <&pgc_mipi>,
+						<&pgc_mipi>;
+				power-domain-names = "bus", "isi",
+						     "lcdif", "mipi-dsi",
+						     "mipi-csi";
+				clocks = <&clk IMX8MN_CLK_DISP_AXI>,
+					 <&clk IMX8MN_CLK_DISP_APB>,
+					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_APB_ROOT>,
+					 <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>,
+					 <&clk IMX8MN_CLK_DSI_CORE>,
+					 <&clk IMX8MN_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MN_CLK_CSI1_PHY_REF>,
+					 <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>;
+				clock-names = "disp_axi", "disp_apb",
+					      "disp_axi_root", "disp_apb_root",
+					      "lcdif-axi", "lcdif-apb", "lcdif-pix",
+					      "dsi-pclk", "dsi-ref",
+					      "csi-aclk", "csi-pclk";
+				#power-domain-cells = <1>;
+			};
+
 			usbotg1: usb@32e40000 {
 				compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
 				reg = <0x32e40000 0x200>;