From patchwork Sat Dec 4 06:10:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Taube X-Patchwork-Id: 12694757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6B249C433F5 for ; Sat, 4 Dec 2021 06:13:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9CaZT2T0IHOwIi1tbR7kHoz8AdaHqqUtNxTopnCfZhM=; b=em+tAiMP5qbrca 3H2BWyeRnOUq8x+/zg1WHzIym8GFmssx3Z7fiBu9CbFQ+0YGXhckd5asniBkysxPsg5OBQ/OXRCFN TmUF33stXrDFS7HJKqXsrjXyH+wG9BXiQtZz4sPmQbi2fRbHIYAaI2Rn4XdbvPCCrHlwiIAevl/pz vhNkff3TVexXgykzOsNHF4bZBFImw12Mft9Ph5bpHeZb6Vf4B3qeyP9O9sL+sEmaNmsfPRlv3Y6U2 xxd+1kbghNvdAc9BbOSJnIMRwCVCjInhFTUdgMWytso5JXPQJ4OzWH+oFJ/yu43vUVNfbDnT047mr +SHUKz52D3n38cnWtcbA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mtOGN-00HY7s-TF; Sat, 04 Dec 2021 06:11:12 +0000 Received: from mail-qt1-x82c.google.com ([2607:f8b0:4864:20::82c]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mtOG0-00HXyG-Lg for linux-arm-kernel@lists.infradead.org; Sat, 04 Dec 2021 06:10:50 +0000 Received: by mail-qt1-x82c.google.com with SMTP id z9so5633857qtj.9 for ; Fri, 03 Dec 2021 22:10:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZZzll1NvlYUi9tw5UeTEbg0jqNcXl/cAUbiZhgavzag=; b=Q4nSugKwo/e7P4oirQJWNn4CEBMcQvnIKD3q5wttbN1uHG/J7kPCIVzzAyy83R4Jj2 N8gARBqv5ZKnu3lepAX9Imp+Wx92Ljy5m/UK4AAmT7dsc63k6AJZa+4WgIDPlr1Y0slG qjT/tTVlLTWRqu/egqfgBzmIEdkyL0d894FV2lytfLMel3CoIq3xuT0dub1kNCT9Bja3 Q7AVrRg4D00jKL4+6HbCpgmcQMdFD/Huc4c7RwQj65Uj8jd3CgaWcTSNZ8vuGO7rX0Jt av6Ebu2FjQL3E6K1kmDmPxO3Oil/moKaRxY3u5ZgIOQDpZkWUvQxrtmVuE5Gy6KzfXYu auTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZZzll1NvlYUi9tw5UeTEbg0jqNcXl/cAUbiZhgavzag=; b=KKIPUEPoafM21f3j7P7RAUCazQce0VL1YmLVegyfb8jF5Npm5CF88xzQWt395jkrSn 4cGRxt92I6kpy1hluHRFMO9tv56BHkXiLZDRXmrfFIhsVOp3G0G75W6qi1LLj4dJzuue 2U4C9zICzvZWy8dx3igKxkk7scBonc9j8AsfSADAcPDk08Pg/VBFYlP9Q/nu0Yg7gdiG 6RJrAd79BigUEAFFih3Aef/IgLC+lBd1wE4b5Kn0xKy/Lm5N4JmSl1Ns0rARkPwbwQNy laDHirx1YQU1v3ydk8BfgQdX/jR2rm3ob4CwcHrmxNEG8E80qqhUO4WSJN/DbVOMyo1Z N4BQ== X-Gm-Message-State: AOAM531MkvTWuV/jRH3D6FsJxSjhf2A33A3xk9igNLx1m55SshSLtrIx 20EjEoSwRDVKXRsNWvrWpTE= X-Google-Smtp-Source: ABdhPJwBe+Bo01JmYoEZJB0UR+he5xjzJib62CqZBZJG4oBKSdY6RlYb5BGngvmTZF7xMc1zlMWRlw== X-Received: by 2002:a05:622a:148:: with SMTP id v8mr25636973qtw.459.1638598247653; Fri, 03 Dec 2021 22:10:47 -0800 (PST) Received: from jesse-desktop.jtp-bos.lab (146-115-144-188.s4282.c3-0.nwt-cbr1.sbo-nwt.ma.cable.rcncustomer.com. [146.115.144.188]) by smtp.gmail.com with ESMTPSA id l1sm3500913qkp.125.2021.12.03.22.10.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Dec 2021 22:10:47 -0800 (PST) From: Jesse Taube X-Google-Original-From: Jesse Taube To: linux-imx@nxp.com Cc: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, ulf.hansson@linaro.org, aisheng.dong@nxp.com, stefan@agner.ch, linus.walleij@linaro.org, gregkh@linuxfoundation.org, arnd@arndb.de, olof@lixom.net, soc@kernel.org, linux@armlinux.org.uk, abel.vesa@nxp.com, adrian.hunter@intel.com, jirislaby@kernel.org, giulio.benetti@benettiengineering.com, nobuhiro1.iwamatsu@toshiba.co.jp, Mr.Bossman075@gmail.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, Jesse Taube , Rob Herring Subject: [PATCH v4 02/13] dt-bindings: pinctrl: add i.MXRT1050 pinctrl binding doc Date: Sat, 4 Dec 2021 01:10:31 -0500 Message-Id: <20211204061042.1248028-3-Mr.Bossman075@gmail.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211204061042.1248028-1-Mr.Bossman075@gmail.com> References: <20211204061042.1248028-1-Mr.Bossman075@gmail.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211203_221048_739527_F5BEA80C X-CRM114-Status: GOOD ( 15.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Jesse Taube Add i.MXRT1050 pinctrl binding doc Cc: Giulio Benetti Signed-off-by: Jesse Taube Reviewed-by: Rob Herring --- V1->V2: * Replace macros with values * Add tab for last pinctrl value V2->V3: * Remove imxrt1050-evk container * Remove unnecessary handles * 2 space tabs to 4 V3->V4: * Nothing done --- .../bindings/pinctrl/fsl,imxrt1050.yaml | 79 +++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml new file mode 100644 index 000000000000..1278f7293560 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IMXRT1050 IOMUX Controller + +maintainers: + - Giulio Benetti + - Jesse Taube + +description: + Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory + for common binding part and usage. + +properties: + compatible: + const: fsl,imxrt1050-iomuxc + + reg: + maxItems: 1 + +# Client device subnode's properties +patternProperties: + 'grp$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + fsl,pins: + description: + each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can + be found in . The last + integer CONFIG is the pad setting value like pull-up on this pin. Please + refer to i.MXRT1050 Reference Manual for detailed CONFIG settings. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: | + "mux_reg" indicates the offset of mux register. + - description: | + "conf_reg" indicates the offset of pad configuration register. + - description: | + "input_reg" indicates the offset of select input register. + - description: | + "mux_val" indicates the mux value to be applied. + - description: | + "input_val" indicates the select input value to be applied. + - description: | + "pad_setting" indicates the pad configuration value to be applied. + + required: + - fsl,pins + + additionalProperties: false + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + iomuxc: iomuxc@401f8000 { + compatible = "fsl,imxrt1050-iomuxc"; + reg = <0x401f8000 0x4000>; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = + <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>, + <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>; + }; + };